part16

Chapter 19: Modern FET Structures

Where this slice sits. This file covers book pages 691-732 (PDF markers 714-755): Chapter 19 (Modern FET Structures), then the Part III closing material (Supplement and Review): the reading list, the cited references, the review list of terms, and the two review problem sets with answers. The Appendices begin right after, so we stop there.

The big picture: what happens when you shrink a transistor?

Picture a garden hose. Open the tap and water flows in a well-behaved way: the valve (your thumb) controls the flow and nothing else interferes. Now shorten the hose to two centimetres. The water no longer “knows” it is in a hose. It sprays, the end of the hose affects the beginning, and your thumb loses some authority.

A MOSFET is that hose. The gate is the thumb, the channel is the hose, and the source and drain are the taps at the two ends. For fifty years the industry has made the hose shorter and shorter to get higher speed (carriers cross a shorter distance) and higher packing density (more transistors per chip). But when the channel becomes comparable to the depletion widths of the source and drain junctions, the source and drain start to interfere with the gate. These departures from the long-channel theory of Chapters 17 and 18 are called small-dimension effects (also short-channel effects or small-geometry effects).

Why should you care? Because:

• The threshold voltage sets logic levels, noise margins, speed and node voltages. If it wanders with channel length, circuits stop working predictably.
• The subthreshold current sets the off-state power dissipation, dynamic-logic clock speeds and DRAM refresh times.

The golden rule of this chapter: small-dimension effects are almost always undesirable. Engineers either avoid them by scaling the device dimensions properly or by redesigning the device. The second half of the chapter is a tour of the redesigned devices (LDD, DMOS, buried-channel, SiGe, SOI, MODFET).

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19.1 Small-Dimension Effects

19.1.1 Introduction

In 1965 the smallest MOSFETs had $L\approx 1\text{mil}=25\mu \text{m}$. By 1990 industry-standard MOS structures were submicron. Figure 19.1 (described: a row of transistor cross sections for the years 1970, 1980, 1990, 2000, each with a visibly shorter gate between the $n^{+}$ source and drain on a $p$ substrate) shows the relative shrinkage of the channel length, which roughly tracks the minimum feature size of production-line MOS DRAMs.

Table 19.1: Silicon IC projections (DRAM = dynamic random access memory; I/O = input/output; wiring levels = number of metallization layers connecting devices on the chip)

Year of first DRAM shipment	1995	1998	2001	2004	2007	2010
Minimum feature size ($\mu$m)	0.35	0.25	0.18	0.13	0.10	0.07
Chip size, microprocessor (mm${}^2$)	250	300	360	430	520	620
Chip size, DRAM (mm${}^2$)	190	280	420	640	960	1400
Bits/chip in DRAMs	64M	256M	1G	4G	16G	64G
Si wafer diameter (mm)	200	200	300	300	400	400
Wiring levels (max, on-chip logic)	4-5	5	5-6	6	6-7	7-8
I/O pads per chip (high performance)	900	1350	2000	2600	3600	4800
Supply voltage, desktop (V)	3.3	2.5	1.8	1.5	1.2	0.9
Supply voltage, portable (V)	2.5	1.8-2.5	0.9-1.8	0.9	0.9	0.9
On-chip frequency, high performance (MHz)	300	450	600	800	1000	1100
Chip-to-board frequency (MHz)	150	200	250	300	375	475

(The OCR printed the feature size as “m”; the unit must be micrometres.) Notice the story the table tells: features shrink, chips grow, but the supply voltage falls only slowly. That last fact matters, because it means the electric fields inside the device grow as dimensions shrink, which is exactly what drives the hot-carrier effects of Section 19.1.4.

Three tell-tale signs of short-channel behaviour

1. Slanted post-pinch-off $I_D$-$V_D$ curves. In a long-channel device the saturated part of the $I_D$-$V_D$ curve is flat. The onset of short-channel effects is heralded by a significant upward slant of the post-pinch-off portion. In severe cases (Fig. 19.2, a device with huge $V_D$ range, 0 to $-30$ V on the axis in the original) the characteristic becomes a family of curves of the form $I_D\propto V_D^2$, and current flows even for gate voltages below threshold. (The Fig. 19.2 device should be “off” for $V_G\le 0$ V, yet it conducts.)

2. Drain-dependent subthreshold current. In a long-channel MOSFET (Fig. 17.11) the subthreshold current varies exponentially with $V_G$ and is independent of $V_D$ as long as $V_D$ exceeds a few $kT/q$. In short-channel devices the subthreshold drain current increases systematically and significantly with $V_D$.

3. Shifts in the threshold voltage. For a long-channel device (Subsection 18.3.1) $V_T$ does not depend on gate length $L$ or width $Z$. In short-channel devices $V_T$ becomes a function of the gate dimensions and of the applied biases (Fig. 19.3: $V_T$ plotted against $L$ from 0 to 7 $\mu$m for $V_D=0.125$ V and $V_D=4$ V; the curves are flat at large $L$ and fall as $L$ shrinks, and the $V_D=4$ V curve falls lower and earlier).

The minimum channel length $L_{min}$

Most small-dimension effects stem from the reduction of $L$. So it is useful to define a minimum channel length below which significant short-channel effects are expected. Crudely, $L_{min}$ must exceed the sum of the source and drain depletion widths; values from 0.1 to 1 $\mu$m result. A better empirical estimate (from computer simulation and experiment) is

L_{min} = 0.4\left[r_j\, x_o\,(W_S + W_D)^2\right]^{1/3} \tag{19.1}

with the unusual units $L_{min}$ in $\mu$m, $r_j$ (source/drain junction depth) in $\mu$m, $x_o$ (oxide thickness) in angstroms, and $W_S$, $W_D$ (depletion widths at the source and drain junctions) in $\mu$m.

What does Eq. (19.1) teach? To make a transistor shorter while keeping long-channel behaviour you can:

• make the source/drain islands shallower (smaller $r_j$),
• make the oxide thinner (smaller $x_o$, so the gate keeps the upper hand),
• dope the substrate more heavily (smaller $W_S$, $W_D$).

All three have actually been used in industry.

Why do departures happen? Three families of causes

1. Broken assumptions. The long-channel theory assumed things (such as a purely one-dimensional field in the channel direction) that are no longer true.
2. Enhanced hidden effects. Effects that always exist but are negligible in long devices become important.
3. Brand-new phenomena. Things like ballistic transport that simply do not appear in long devices.

All three families are represented below.

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19.1.2 Threshold Voltage Modification

Short channel: the source and drain “help” the gate

In enhancement-mode devices $V_T$ decreases monotonically as $L$ decreases.

Intuition (a tug-of-war over charge). Before inversion the region under the gate must be depleted, i.e. depletion charge $-q{N}_A{W}_T$ per unit area must be balanced by positive charge somewhere. In a long device all of it is balanced by gate charge. In a short device the source and drain $pn$ junctions already own a depletion layer of their own; a fraction of the “subgate” depletion charge is balanced by charge on the other side of the source and drain junctions (the $n^{+}$ islands). Think of two neighbours both contributing to pay a shared bill: the gate pays less. Less gate charge is needed to reach the start of inversion, so $|V_T|$ drops. The shorter the channel, the larger the percentage borne by the junctions, and the bigger the reduction.

Derivation of $\Delta V_T$ (short channel)

Step 1: ideal MOS-C voltage balance. For an ideal device

V_G = V_{ox} + \phi_s, \qquad V_{ox} = \frac{|Q_G|\,}{C_o}\ \text{(magnitude)}\quad \Rightarrow\quad V_G = -\frac{Q_s}{C_o} + \phi_s \tag{19.2--19.4}

where $C_o=K_O{ϵ}_0/x_o$ and $Q_s$ is the total charge per cm${}^2$ inside the semiconductor. (Gauss’ law gives $Q_s=-K_S{ϵ}_0{\mathcal{E}}_s$ and, combined with the oxide field, yields the voltage balance above, with the gate charge equal and opposite to $Q_s$.)

Step 2: specialize to threshold. At the start of inversion ${\varphi }_s=2{\varphi }_F$ and $Q_s\to Q_B$ (the depletion, or bulk, charge per unit area of gate):

V_T = 2\phi_F - \frac{Q_B}{C_o} \tag{19.5}

Step 3: define the shift.

\Delta V_T = V_T(\text{short channel}) - V_T(\text{long channel}) \tag{19.6}

Let $Q_{BL}$ and $Q_{BS}$ be the depletion charges per cm${}^2$ in the long- and short-channel device. Because $2{\varphi }_F$ cancels in the difference:

\Delta V_T = -\frac{1}{C_o}\left(Q_{BS} - Q_{BL}\right) = -\frac{Q_{BL}}{C_o}\left(\frac{Q_{BS}}{Q_{BL}} - 1\right) \tag{19.7}

Step 4: depletion charge of a long device. Take $V_D$ small or zero so that $W_s\le W_T$ everywhere under the gate; call $W=W_T$. The gate controls the whole rectangular depletion volume $ZLW$ ($Z$ = gate width). Dividing the charge by gate area $ZL$:

Q_{BL} = \frac{-qN_A (ZLW)}{ZL} = -qN_A W \tag{19.8}

Step 5: depletion charge of a short device. The portions near the source and drain (shaded in Fig. 19.4: two triangles at the bottom corners of the rectangle, bounded by the circular-looking junction depletion edges) are controlled by the source and drain. The gate controls only the trapezoid with top side $L$ and bottom side $L^{\prime }$, whose area (per unit $Z$) is $\frac{1}{2}(L+L^{\prime })W$:

Q_{BS} = \frac{-qN_A \tfrac12 (L + L')\,Z\,W}{ZL} = -qN_A W\,\frac{L + L'}{2L} \tag{19.9}

Step 6: assemble. Substitute (19.8) and (19.9) in (19.7):

\Delta V_T = -\frac{qN_A W}{C_o}\left[1 - \frac{L + L'}{2L}\right] \tag{19.10}

Step 7: geometry for $L^{\prime }$. Model each junction corner as a quarter-cylinder of radius $r_j$ (centre on the surface at the lateral edge of the island, a distance $r_j$ outward) with the depletion edge a concentric arc of radius $r_j+W$ (taking $W_S=W_D=W$). The arc crosses the depth $y=W$ (the bottom of the gate-controlled depletion layer) at horizontal distance $\sqrt{(r_j+W{)}^2-W^2}$ from the centre, i.e. at lateral distance $\Delta$ inside the channel edge, where

(r_j + W)^2 = (r_j + \Delta)^2 + W^2 \tag{19.11}

Solving: $r_j+\Delta =\sqrt{r_j^2+2r_{j}W}$, so $\Delta =r_j\left[\sqrt{1+2W/r_j}-1\right]$. Both ends of the bottom side lose $\Delta$:

L' = L - 2\Delta = L - 2r_j\left[\sqrt{1 + \frac{2W}{r_j}} - 1\right] \tag{19.12}

Step 8: final result. Since $\frac{L+L^{\prime }}{2L}=1-\frac{\Delta }{L}$, we have $1-\frac{L+L^{\prime }}{2L}=\frac{\Delta }{L}$, and Eq. (19.10) becomes

\boxed{\Delta V_T(\text{short channel}) = -\frac{qN_A W_T}{C_o}\,\frac{r_j}{L}\left[\sqrt{1 + \frac{2W_T}{r_j}} - 1\right]} \tag{19.13}

(with $W=W_T$ at threshold).

Reading the result. The magnitude of the shift is large when $r_j/L$ is large, i.e. when the junctions are deep compared with the gate length. Examining $\Delta V_T/V_T(\text{long channel})$, the relevant gauge of importance, the effects are again minimized by reducing $x_o$ (raising $C_o$), reducing $r_j$, and increasing $N_A$ (which shrinks $W_T$ more than it raises $q{N}_A$). This is the same list as for $L_{min}$: a nice consistency check on a first-order derivation.

Narrow width: the gate also gets help from the sides

For $Z$ comparable to $W_T$, $V_T$ increases as $Z$ decreases. The $Z$-dependence is opposite to the $L$-dependence.

Intuition. Look at the side view (Fig. 19.5: gate oxide over the channel, thick field oxide on each side, and a depletion region that bulges out sideways under the field oxide beyond the gate width $Z$). The gate field also fringes sideways and has to balance that extra lateral depletion charge. In a wide device this fringe is negligible. In a narrow one it is comparable to the charge right under the gate. More charge per unit gate area means more gate voltage to reach inversion, so $V_T$ rises.

Derivation. Take the two lateral regions as quarter-cylinders of radius $W$. Their combined volume is $2\cdot \frac{1}{4}\pi W^{2}L=\frac{\pi }{2}{W}^{2}L$. The total controlled volume is $ZLW+\frac{\pi }{2}{W}^{2}L$:

Q_B(\text{narrow}) = \frac{-qN_A\left(ZLW + \tfrac{\pi}{2}W^2 L\right)}{ZL} = -qN_A W\left(1 + \frac{\pi W}{2Z}\right) \tag{19.14}

Replace $Q_{BS}$ by this in Eq. (19.7), with $Q_{BL}=-q{N}_{A}W$:

$\Delta V_T=-\frac{1}{C_o}\left[Q_B(\text{narrow})-Q_{BL}\right]=+\frac{q{N}_{A}W}{C_o}\cdot \frac{\pi W}{2Z}$

\boxed{\Delta V_T(\text{narrow width}) = \frac{qN_A W_T}{C_o}\,\frac{\pi W_T}{2Z}} \tag{19.15}

This confirms the initial claim: it becomes important when $Z\sim W_T$.

Combined effects. A MOSFET with both a short channel and narrow width has a combined $\Delta V_T$ that is not simply the sum of the two individual shifts; more exact expressions are in the literature (DeMassa and Chien, ref. 30).

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19.1.3 Parasitic BJT Action

A MOSFET has an oppositely doped region between source and drain: $n^{+}$-$p$-$n^{+}$. That is a lateral NPN bipolar transistor! (The source is the emitter, the substrate the base, the drain the collector.) When $L$ shrinks to the size of a BJT base width, bipolar phenomena show up.

Source-to-drain punch-through. When source and drain are a few microns or less apart, their depletion regions can touch (Fig. 19.6: two $n^{+}$ islands with depletion boundaries merged beneath the gate). The gate then loses control of the subgate region except for a thin skin at the Si-SiO${}_2$ interface. Current is no longer confined to the surface channel; it flows beneath the surface through the touching depletion regions as a space-charge-limited current, which (as in BJT punch-through) varies as the square of the applied source-drain voltage, $I\propto V_D^2$. The $V_G\le 0$ characteristics in Fig. 19.2 are examples of this $I\propto V^2$ behaviour.

Cure: raise the subgate doping, which narrows the depletion widths. But a heavier entire substrate raises parasitic capacitances, so the standard practice is a deep ion implant that selectively dopes only the subgate region.

Carrier multiplication with regenerative feedback. There is always a little impact ionization in the high-field region near the drain. In long devices it is negligible; in short ones, coupled with regenerative feedback, it can dramatically raise the drain current, reduce the maximum usable $V_D$, and even destroy the device. The mechanism (Fig. 19.7) is just like the lowering of $B{V}_{CEO}$ relative to $B{V}_{CBO}$ in a BJT (Subsection 11.2.4):

1. Channel current enters the high-field drain region. A small fraction of carriers gains enough energy to create electron-hole pairs by impact ionization.
2. For an $n$-channel device the new electrons drift into the drain; the new holes are swept into the quasi-neutral bulk.
3. The hole current flowing through the finite bulk resistance $R_{BB}$ produces a potential drop between the depletion edge and the back contact, of polarity that forward biases the source $pn$ junction.
4. A forward-biased source junction injects electrons into the bulk, which add to the electron flow into the drain, giving more multiplication, and so on.

The process is stable while the multiplication factor (the fractional increase in drain current) is less than $1/\alpha$, with $\alpha$ the common-base gain of the parasitic BJT. Beyond that, the current runs away and the device can fail.

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19.1.4 Hot-Carrier Effects

Hot carriers are carriers with far more kinetic energy than the lattice thermal energy $kT$, picked up from large electric fields.

Oxide charging. Near the drain, channel carriers (and carriers entering the drain depletion region from the substrate) occasionally gain enough energy to jump over the Si-SiO${}_2$ barrier (about 3.1 eV for electrons) and enter the oxide. Neutral traps in the oxide capture part of that charge, and the oxide slowly charges up. In long devices this explains “walk-out” (a progressive rise of the drain breakdown voltage with operation at large $V_D$). In short devices it is much worse because a larger fraction of the gated region is affected: $V_T$, $g_m$ and other parameters can change significantly. And since the charging is cumulative, it limits the useful lifetime of a device. A popular remedy is the lightly doped drain (Subsection 19.2.1).

Velocity saturation. The long-channel analysis implicitly assumed that carrier velocity rises without limit as needed to support the current. In reality drift velocity saturates at $v_{sat}\approx 10^7$ cm/s when the field exceeds about $3\times 10^4$ V/cm for electrons and about $10^5$ V/cm for holes (Fig. 3.4, Part I). Example: $V_D=2$ V across $L=0.5\mu$m gives an average field of $2/(0.5\times 10^{-4})=4\times 10^4$ V/cm, so there are certainly places in the channel at or beyond saturation.

Two effects on the characteristics:

1. $I_{Dsat}$ is significantly reduced, modified approximately to

I_{Dsat} \approx Z\, C_o\,(V_G - V_T)\,v_{sat} \tag{19.16}

Why this form? Saturation current = (charge per unit area in the channel) $\times$ (width) $\times$ (velocity); the inversion charge is $C_o(V_G-V_T)$ and the velocity is pinned at $v_{sat}$.

2. As Eq. (19.16) shows, $I_{Dsat}$ depends almost linearly on $V_G-V_T$ instead of with the long-channel square law. Fig. 19.8 shows (a) the experimental curves of a short device ($L=2.7\mu$m, with evenly spaced curves for $V_G$ = 1, 2, 3, 4, 5 V), (b) a theory including velocity saturation (evenly spaced, matches the data) and (c) a theory ignoring it (spacing growing quadratically, does not match). Diagnostic: if equal steps in $V_G$ give roughly equal steps in $I_{Dsat}$ you are looking at velocity saturation; if the steps grow with $V_G$ it is square-law.

Velocity overshoot and ballistic transport. The long-channel model assumed many scattering events between source and drain: $L\gg \ell$, where $\ell$ is the mean free path (average distance between scatterings). When $L\lesssim \ell$ a large fraction of carriers travels from source to drain without a single scattering: projectile-like, or ballistic, motion. Observable ballistic effects are theoretically possible in GaAs for $L\le 0.3\mu$m (somewhat shorter in Si). Both Si and GaAs FETs with $L\sim 0.1\mu$m have been built in research labs, and Table 19.1 says such devices become commonplace.

Why care? With reduced scattering the average velocity through the channel can exceed $v_{sat}$: velocity overshoot. Average velocities up to 35% above $v_{sat}$ have been seen in a $0.12\mu$m MOSFET (ref. 32, Assaderaghi, Ko and Hu). Other limits (such as the injecting capability of the source) remain, but ballistic effects have been observed and will matter in future FETs.

Analogy. A crowd moving through a corridor: if people keep bumping into one another (scattering) their average speed is capped. In a corridor so short that nobody bumps into anybody, everybody just runs.

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19.2 Select Structure Survey

The basic enhancement-mode MOSFET is the right model for learning concepts. In industry there are many variations to solve specific problems or to enhance specific characteristics, and compound-semiconductor FETs (GaAs and others) look somewhat different from Si ones. This survey is only a sample, biased toward structures common in the recent literature.

19.2.1 MOSFET Structures

LDD (lightly doped drain) transistors

Small devices are more susceptible to hot carriers, especially because supply voltages were not scaled down in proportion to dimensions. In the LDD structure (Fig. 19.9: poly-Si gate with sidewall oxide spacers, $n^{-}$ lightly doped regions between the channel end and the $n^{+}$ source and drain), the $n^{-}$ region creates a reduced doping gradient going from channel to drain. This lowers the peak electric field near the drain and shifts the peak toward the end of the channel, away from the oxide edge. Less carrier injection into the oxide, less oxide charging. (It is like replacing a sudden cliff by a gentle slope: the water, here the field, is spread out.)

DMOS (double-diffused MOSFET)

(Fig. 19.10: a vertically structured transistor with $n^{+}$ source inside a $p$ region, in an $n^{-}$ epitaxial layer; the channel is the lateral difference between the two diffusions; the lateral doping profile $N_D-N_A$ is plotted along $x$.)

A $p$-type dopant (boron) is introduced first, then an $n$-type dopant (phosphorus), both through the same oxide mask opening. Boron diffuses slightly deeper and farther to the side. The channel length is the lateral difference of the two profiles, so a short channel ($\sim 1\mu$m) is achieved without small-dimension lithography. The result is high-frequency operation combined with high drain breakdown voltage (the lightly doped $n^{-}$ drain drift region supports voltage). Used in high-frequency analog and high-voltage/high-power circuits; introduced in the early 1970s; power-DMOS variants continue to be developed.

Buried-channel MOSFET

(Fig. 19.11: the same transistor with a thin $n$-type surface layer under the gate, same type as source and drain, doping $N_D$ on top of the $p$ body $N_A$; the sketched profile shows $N_D$ in the thin layer and $-N_A$ below.)

The surface layer, typically ion-implanted, forms a $pn$ junction bottom gate and an MOS top gate: physically and functionally a hybrid J-FET/MOSFET. Depending on the thickness and doping of the layer it can be designed as depletion-mode or enhancement-mode. The name arises because conduction can take place away from the oxide-semiconductor interface. Benefits: inherently higher mobility (no interface scattering), reduced interface-trap interaction, and reduced sensitivity to hot-carrier effects.

SiGe devices

Ultrahigh-vacuum chemical-vapor deposition (UHV/CVD, ref. 35) allows production-line deposition of high-quality Si${}_{1-x}$Ge${}_x$ films: atomic-level thickness control, precise composition, minimal background contamination, any Ge fraction from 0 to 100%.

Lattice constants: Ge is $a=5.65$ Å, Si is $a=5.43$ Å, so a relaxed SiGe alloy has a lattice constant larger than Si. But if a SiGe film on Si is thin enough (typically $\le 1000$ Å) it is pseudomorphic: it conforms atom by atom to the lattice of the Si substrate (and is therefore compressed in-plane). SiGe-base heterojunction bipolar transistors (HBTs) built this way achieved the highest operating frequency of any Si bipolar device.

Pseudomorphic films carry large internal stress. Beyond a critical thickness defects nucleate spontaneously, relieve stress, and the film relaxes to its preferred lattice constant. Relaxed SiGe films are valuable for enhanced-mobility MOSFETs (Fig. 19.12): on a Si substrate grow (1) a compositionally graded SiGe buffer layer (5% to 30% Ge, about 1.5 $\mu$m), (2) a relaxed Si${}_{0.7}$Ge${}_{0.3}$ layer (about 0.25 $\mu$m), and (3) a thin (about 6 nm) pseudomorphic strained Si layer, topped with a 12 nm SiO${}_2$ gate oxide and $n^{+}$ poly-Si gate. The defects are confined to the buffer; the relaxed Si${}_{0.7}$Ge${}_{0.3}$ acts as a quality substrate. Matching its larger lattice constant stretches the Si film (tension), which reduces carrier scattering and lowers the electron effective mass parallel to the interface. Both raise the mobility: the pictured device showed about a factor 2 enhancement of low-field mobility over a standard MOSFET, translating to more current drive at high fields and extending the performance limits of MOS technology.

SOI (silicon-on-insulator) structures

SOI = devices fabricated in single-crystal Si layers on an insulating film or substrate. Historical routes:

• SOS (silicon on sapphire): Si deposited on properly oriented sapphire.
• Laser recrystallization of amorphous Si on SiO${}_2$ or Si${}_3$N${}_4$.
• ELO (epitaxial layer overgrowth): open a hole in the insulator to expose the Si substrate; it acts as a seed; epitaxial Si grows up through the hole and sideways over the insulator. Good film quality but not a production-line technology.

Only SIMOX and BESOI are production-line technologies giving acceptable-quality films, and both wafer types are sold commercially.

• BESOI (Bonded and Etched-back SOI): thermally grow SiO${}_2$ on one Si wafer (this becomes the insulator), bond a second wafer on top and anneal, then grind, polish and chemically etch the top wafer down to the desired thickness.
• SIMOX (Separation by IMplantation of OXygen; Fig. 19.13 process flow: implant oxygen into Si, anneal to form SiO${}_2$, optionally grow CVD epi to the required Si thickness). Oxygen implant energy 150-200 keV, total dose $1$-$2\times 10^{18}$ atoms/cm${}^2$. Anneal at about $1300^{\circ }$C for roughly 6 hours so the oxygen reacts with Si to form a buried oxide (BOX) and the surface Si heals. Additional epitaxial Si may be added. Required Si thickness: 500-2000 Å for CMOS and 0.3-10 $\mu$m for thick-film bipolar.

Projected advantages of SOI: dielectric isolation of devices reduces parasitic capacitance (higher speed) and totally eliminates latch-up (a CMOS failure mode where the circuit gets stuck in a specific state through parasitic thyristor-like action); lower power; higher-temperature operation; better radiation hardness; reduced short-channel effects; higher packing density and easier scaling; simpler processing with fewer masking steps; and wafers fully compatible with production equipment. Most extensive use so far: radiation-hardened SRAMs for military use. Expected growth: very high speed VLSI CMOS, low-supply-voltage devices, DRAMs.

19.2.2 MODFET (HEMT)

The modulation doped field effect transistor. Alternate names: HEMT (high electron mobility transistor), SDHT (selectively doped heterostructure transistor), TEGFET (two-dimensional electron-gas FET). (Note: the HEMT name persists, but it is now recognized that the low-field mobility is not the key parameter in normal operation. As with the MESFET of Section 15.3, the high-field velocity is critical when large fields exist along the channel.)

Structure (Fig. 19.14a: from top, Schottky gate between source and drain ohmic contacts, $n^{+}$-GaAs cap layer, $n$-AlGaAs, nominally undoped GaAs, semi-insulating GaAs substrate). If you think of the AlGaAs as an insulator, the MODFET resembles a MOSFET. Differences: the “insulator” AlGaAs is doped, and the GaAs epilayer is nominally undoped. “Modulation doping” means the dopant source is modulated during the sequential deposition so that only the AlGaAs is doped. The doping induces a surface channel next to the AlGaAs/GaAs interface. Since the current-carrying GaAs is undoped, there is minimal scattering from residual impurities: very high room-temperature electron mobility, and an even greater improvement at liquid-nitrogen temperature relative to doped-channel devices such as MESFETs. Hence the name.

Energy bands (Fig. 19.14b: Schottky metal, depleted $n$-AlGaAs, undoped GaAs; a triangular quantum well of the inversion layer, the 2DEG, at the interface; $\Delta E_C$ is the conduction-band offset). AlGaAs has a wider gap, so band offsets appear at the interface (as in Fig. 11.19a), and $\Delta E_C$ acts as an electron-containment barrier. The AlGaAs is thin enough to be totally depleted at equilibrium by the Schottky built-in potential. The leftover uncompensated donors in the AlGaAs produce a band diagram very similar to a MOSFET with sodium ions distributed through the oxide (compare Fig. 19.14b with Fig. P18.7). Also, AlGaAs/GaAs is lattice-matched, so the interface is essentially free of fixed charge and interface traps, a prerequisite of good operation.

Limitation and second generation. Above a certain carrier density the relatively small $\Delta E_C$ lets channel charge spill over into the AlGaAs. The channel density then saturates versus gate potential and performance degrades at moderate and high currents. Two solutions:

1. PHEMT (pseudomorphic HEMT): put a pseudomorphic In${}_x$Ga${}_{1-x}$As layer between the AlGaAs and the GaAs (Fig. 19.15). Adding In lowers the gap and increases the containment barrier $\Delta E_C$, allowing higher carrier densities in the InGaAs channel. Fig. 19.15: a Hewlett-Packard commercial PHEMT with $n^{+}$-GaAs, $n$-AlGaAs, InGaAs and undoped GaAs on a semi-insulating GaAs substrate, T-shaped Au gate.
2. Lattice-matched on InP: the In${}_{0.52}$Al${}_{0.48}$As/In${}_{0.53}$Ga${}_{0.47}$As system, InP as substrate. $\Delta E_C$ there is roughly twice that of AlGaAs/GaAs. Still immature, but already gives the best high-frequency performance of three-terminal devices.

The T gate. At routine submicron gate lengths, parasitic resistances often mask intrinsic performance. The mushroom (“T”) gate keeps a small footprint (short $L$) while increasing the metal cross-section and hence reducing gate resistance.

Status. The MODFET gradually replaces GaAs MESFETs in advanced commercial and military systems that need ultra-high performance, and is ideal for low-noise amplification at microwave and millimetre-wave frequencies. Although conceived as an ultra-high-speed digital device, it is now unlikely to displace Si devices in the near future.

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Chapter 19 Summary (key results at a glance)

Topic	Key result
Short-channel signs	slanted saturation, $V_D$-dependent subthreshold current, $V_T$ shift
$L_{min}$	$0.4[r_j{x}_o(W_S+W_D{)}^2{]}^{1/3}$ ($\mu$m; $r_j$ in $\mu$m, $x_o$ in Å)
Short-channel $\Delta V_T$	$-\frac{q{N}_A{W}_T}{C_o}\frac{r_j}{L}\left[\sqrt{1+2W_T/r_j}-1\right]$
Narrow-width $\Delta V_T$	$+\frac{q{N}_A{W}_T}{C_o}\frac{\pi W_T}{2Z}$
Punch-through	$I\propto V^2$ space-charge current; cured by deep implant
Multiplication feedback	stable while $M<1/\alpha$
Velocity saturation	$I_{Dsat}\approx Z{C}_o(V_G-V_T)v_{sat}$
Ballistic/overshoot	$L\lesssim \ell$; velocities up to $\sim$35% above $v_{sat}$ seen
Structures	LDD (less hot-carrier), DMOS (short $L$ without fine lithography), buried-channel, strained-Si, SOI (SIMOX, BESOI), MODFET/PHEMT

Computer-based exercises: Chapter 19 contains none.

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Chapter 19 Problems

Problem information table (from the book): 19.1 Quick quiz (after 19.2.2, level 1, 15 points); 19.2 Acronyms (after 19.2.2, level 1, 5 points); 19.3 $L_{min}$ and $\Delta V_T$ calculations (after 19.1.2, level 2-3, 12 points); 19.4 Identify unique features (after 19.2.1, level 1, 10 points); 19.5 Summarize journal articles (after 19.2.2, level 2-3, 30 points).

19.1 Quick Quiz

(a) Small-dimension effects are generally undesirable and are minimized or avoided in commercial MOSFETs by proper scaling or design modifications. True or false? True. Short-channel effects shift $V_T$ and raise off-current, so scaling rules and designs like LDD, retrograde implants and shallow junctions suppress them.

(b) Three most common indications of short-channel effects. (1) Upward slant of the post-pinch-off $I_D$-$V_D$ curves; (2) a subthreshold current that increases with $V_D$; (3) a threshold voltage that depends on gate dimensions and biases.

(c) How do short-channel and narrow-width threshold modifications differ, and how are they alike? Different: short channel lowers $V_T$ (decreasing $L$), narrow width raises $V_T$ (decreasing $Z$). Alike: both arise from charge that the gate does not “own” as simple rectangular volume under it; in the short channel, source/drain junctions balance part of the depletion charge (less gate charge needed), in the narrow device fringing depletion on the sides adds extra charge the gate must balance. Both become important when the dimension ($L$ or $Z$) is comparable to the depletion width, and both are treated with the same geometric (charge-sharing) method.

(d) For fixed $L$ and $Z$, two other parameters that can be adjusted, and how. Reduce the junction depth $r_j$ (shallower source/drain), reduce the oxide thickness $x_o$, or increase the substrate doping $N_A$ (all reduce $L_{min}$ and $\Delta V_T$). Give any two.

(e) Two BJT-like phenomena in short-channel MOSFETs. Source-to-drain punch-through (space-charge current) and parasitic-BJT carrier multiplication with regenerative feedback (substrate-current-induced source-junction forward bias).

(f) What happens in oxide charging? Near the drain, hot channel carriers (and carriers from the drain depletion region) gain enough energy to surmount the Si-SiO${}_2$ barrier and enter the oxide; neutral traps there capture part of them, so charge builds up in the oxide, shifting $V_T$ and degrading device parameters.

(g) Why is oxide charging more important in short-channel devices? The same drain-region injection affects a larger percentage of the gated region when the channel is short, and fields are higher because voltages were not scaled down in proportion; the effect is also cumulative, limiting lifetime.

(h) How can you tell if velocity saturation is affecting $I_D$-$V_D$ characteristics? The saturation current varies nearly linearly with $V_G-V_T$ (equal $V_G$ steps give nearly equal $I_{Dsat}$ steps) and $I_{Dsat}$ is lower than the square-law prediction.

(i) Ballistic transport. Carriers travel source to drain with essentially no scattering (projectile-like motion), possible when $L\lesssim \ell$, the mean free path.

(j) Velocity overshoot. With reduced scattering, the average carrier velocity in the channel exceeds the steady-state saturation velocity $v_{sat}$.

(k) A popular approach to minimize oxide charging. The lightly doped drain (LDD) structure.

(l) What is a pseudomorphic film? A sufficiently thin (typically $\le 1000$ Å) epitaxial film of a lattice-mismatched alloy (e.g. SiGe on Si) that conforms atom by atom to the lattice of the substrate, and so is strained rather than relaxed.

(m) Two examples of pseudomorphic films in devices. The pseudomorphic SiGe base layer of Si heterojunction bipolar transistors, the strained-Si surface channel of the enhanced-mobility MOSFET, and the InGaAs channel layer of the PHEMT.

(n) Briefly summarize SIMOX. Implant oxygen (150-200 keV, dose $1$-$2\times 10^{18}$ cm${}^{-2}$) below the Si surface; anneal (about $1300^{\circ }$C, 6 h) so the oxygen reacts to form a buried SiO${}_2$ layer and the surface Si recovers; optionally add epitaxial Si for thickness.

(o) MODFET versus HEMT. No physical difference: they are two names for the same device. MODFET emphasizes modulation doping; HEMT emphasizes high electron mobility.

19.2 Acronyms and abbreviations

Acronym	Meaning
LDD	lightly doped drain
DMOS	double-diffused MOS (field-effect transistor)
SOI	silicon-on-insulator
SOS	silicon-on-sapphire
ELO	epitaxial layer overgrowth
SIMOX	separation by implantation of oxygen
BESOI	bonded and etched-back silicon-on-insulator
BOX	buried oxide
MODFET	modulation-doped field-effect transistor
PHEMT	pseudomorphic high electron mobility transistor

19.3 $L_{min}$ and $\Delta V_T$ for the Fig. 19.3 device

Problem. Fig. 19.3 device: $N_A=8\times 10^{16}$ cm${}^{-3}$ (the OCR lost the exponent; $10^{16}$ is the value consistent with a 280 Å oxide device and the plotted $V_T$ range), $x_o=0.028\mu$m $=280$ Å, $r_j=1\mu$m. (a) Use Eq. (19.1) to compute the expected $L_{min}$ for $V_D=0.125$ V (assume $n^{+}$-$p$ step junctions, source and back grounded; comment). (b) Use Eq. (19.13) to find $\Delta V_T$ at $L=1\mu$m, $V_D=0.125$ V. (c) (The OCR dropped this part; it asks whether Eq. (19.13) can explain the $V_D=4$ V data of Fig. 19.3.)

Assumptions. $n_i=10^{10}$ cm${}^{-3}$ at 300 K, $K_S=11.8$, $K_O=3.9$, ${ϵ}_0=8.85\times 10^{-14}$ F/cm, $n^{+}$ doping $N_D=10^{20}$ cm${}^{-3}$ (so only $N_A$ matters in $W$).

Solution (a).

Built-in potential: $V_{bi}=\frac{kT}{q}\ln \frac{N_A{N}_D}{n_i^2}=0.0259\ln \frac{(8\times 10^{16})(10^{20})}{10^{20}}=0.0259(38.92)=1.01\text{V}$

Source depletion width ($V_S=0$): $W_S={\left[\frac{2K_S{ϵ}_0{V}_{bi}}{q{N}_A}\right]}^{1/2}={\left[\frac{2(11.8)(8.85\times 10^{-14})(1.01)}{(1.6\times 10^{-19})(8\times 10^{16})}\right]}^{1/2}={\left[1.65\times 10^{-10}\right]}^{1/2}=1.28\times 10^{-5}\text{cm}=0.128\mu \text{m}$

Drain depletion width (reverse bias $V_D=0.125$ V): $W_D=W_S\sqrt{\frac{V_{bi}+V_D}{V_{bi}}}=0.128\sqrt{\frac{1.135}{1.01}}=0.136\mu \text{m}$

Sum: $W_S+W_D=0.264\mu$m. Then $r_j{x}_o(W_S+W_D{)}^2=(1)(280)(0.264{)}^2=19.5$ $L_{min}=0.4(19.5{)}^{1/3}=0.4(2.69)=1.08\mu \text{m}$

Comment. $L_{min}\approx 1\mu$m. In Fig. 19.3 the $V_T$ curves are essentially flat for $L\gtrsim 3$-$4\mu$m and fall off as $L$ approaches $\sim 1\mu$m and below, which agrees with $L_{min}$ marking the onset of significant short-channel effects.

Solution (b).

$2{\varphi }_F=2(0.0259)\ln \frac{8\times 10^{16}}{10^{10}}=2(0.0259)(22.80)=1.18\text{V}$ $W_T={\left[\frac{2K_S{ϵ}_0(2{\varphi }_F)}{q{N}_A}\right]}^{1/2}={\left[\frac{2(11.8)(8.85\times 10^{-14})(1.18)}{(1.6\times 10^{-19})(8\times 10^{16})}\right]}^{1/2}=1.39\times 10^{-5}\text{cm}=0.139\mu \text{m}$ $C_o=\frac{K_O{ϵ}_0}{x_o}=\frac{(3.9)(8.85\times 10^{-14})}{2.8\times 10^{-6}}=1.23\times 10^{-7}{\text{F/cm}}^2$ $\frac{q{N}_A{W}_T}{C_o}=\frac{(1.6\times 10^{-19})(8\times 10^{16})(1.39\times 10^{-5})}{1.23\times 10^{-7}}=1.45\text{V}$ $\frac{r_j}{L}=1,\sqrt{1+\frac{2W_T}{r_j}}-1=\sqrt{1+0.278}-1=0.130$ $\Delta V_T=-(1.45)(1)(0.130)\approx -0.19\text{V}$

So $V_T$ is about 0.19 V below its long-channel value at $L=1\mu$m.

Solution (c). Eq. (19.13) contains no $V_D$ dependence; it was derived for $V_D\approx 0$ so that $W_S\approx W_D$. Therefore it predicts the same $\Delta V_T$ for $V_D=4$ V as for $0.125$ V and cannot explain the larger decrease seen in the $V_D=4$ V data. Physically, a large $V_D$ widens the drain depletion region ($W_D$ grows), so the drain controls a larger share of the subgate charge (the trapezoid becomes more lopsided) and $|V_T|$ falls more. A better model would use $W_D(V_D)$ in the geometry.

19.4 Unique physical nature of the structures

(a) LDD: a lightly doped $n^{-}$ region between the channel end and the $n^{+}$ drain (and source), giving a lower doping gradient, lower peak field shifted away from the oxide edge, less hot-carrier injection. (b) DMOS: channel formed and its length set by the lateral difference of two diffusions (boron then phosphorus) through the same mask opening, giving a short channel without fine lithography and a high breakdown voltage. (c) Buried-channel MOSFET: a thin surface layer of the same type as source/drain under the gate; conduction occurs below the interface in a hybrid J-FET/MOSFET structure with higher mobility and fewer interface effects. (d) Enhanced-mobility (strained-Si) MOSFET: a thin pseudomorphic strained-Si channel grown on relaxed Si${}_{0.7}$Ge${}_{0.3}$ over a graded SiGe buffer; tensile strain lowers scattering and effective mass, roughly doubling low-field mobility. (e) SOI: devices built in a thin single-crystal Si layer on an insulator (e.g. buried oxide), giving dielectric isolation, low parasitic capacitance, no latch-up, radiation hardness.

19.5 Journal article summaries

This problem asks the reader to read six papers and write one-to-two-page summaries; the articles are not reproduced here, so below is a short orientation for each, based on the titles and the chapter’s own discussion (the reader should still read the articles for the actual summaries).

(a) Sanchez, Hsueh, DeMassa, Drain-Engineered Hot-Electron-Resistant Device Structures: A Review (1989): surveys drain structures (LDD, graded drain, double-diffused drain, etc.) that lower the peak drain field to suppress hot-electron injection and oxide charging. (b) Van der Tol and Chamberlain, Potential and Electron Distribution Model for the Buried-Channel MOSFET (1989): models the electrostatics of the Fig. 19.11 structure, the potential in the implanted layer, and where the electrons sit (surface versus buried) as a function of gate bias. (c) Meyerson, UHV/CVD Growth of Si and Si:Ge Alloys (1992): the chemistry and physics of the low-temperature, ultrahigh-vacuum CVD process and the HBT and other devices it enables. (d) Meyerson, Ultrahigh-Vacuum CVD Process Makes SiGe Devices (1994): a shorter, process-oriented account of the same technology. (e) Peters, SOI Takes Over Where Silicon Leaves Off (1993): an industry overview of SOI materials (SIMOX, BESOI), advantages and applications. (f) Nguyen, Larson, Mishra, Ultra-High-Speed Modulation-Doped FETs: A Tutorial Review (1992): covers modulation doping, 2DEG physics, AlGaAs/GaAs, PHEMT and InP-based devices, and the limits on speed (high-field velocity, parasitics).