part14

Chapter 17: MOSFETs — The Essentials

Source slice: Pierret, Semiconductor Device Fundamentals, Chapter 17 (book pp. 611–644). The OCR was noisy; garbled symbols have been repaired from physics knowledge. Where a figure is missing, its content is described.

Imagine a garden hose. You do not push water by hand through the hose. You step on it, and the squeeze controls the flow. A MOSFET is the same idea in silicon. The gate is your foot. The source is the tap. The drain is the open end. The “hose” is a thin sheet of electrons that the gate itself creates from nothing. Billions of these tiny taps, switched on and off, make up every phone and laptop processor. This chapter explains how one of them works.

Historical note on names: the device was once called MOST, IGFET, MOSFET, and even PIGFET and MISFET. The name MOSFET (metal-oxide-semiconductor field-effect transistor) won. We keep assuming an ideal MOS structure (no oxide charge, no work-function difference, no interface traps). We study the basic long-channel enhancement-mode device. Small-dimension effects come in Chapter 19, and non-idealities in Chapter 18.

Plan of the chapter:

1. Qualitative theory of operation (what happens inside, in pictures).
2. Quantitative $I_D$–$V_D$ relationships (square-law theory and bulk-charge theory, and a glance at charge-sheet and exact-charge theories).
3. a.c. response (small-signal circuits, cutoff frequency, characteristics).

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17.1 Qualitative Theory of Operation

The structure

A MOSFET is, physically, an MOS capacitor with two pn junctions placed immediately next to the gated region. Figure 17.1 shows it. Take a p-type silicon substrate (an n-channel device):

• Two heavily doped $n^{+}$ islands, the source (S) and the drain (D), are diffused or implanted in the surface.
• Between them sits the gate (G): metal (or polysilicon) on top of a thin ${\text{SiO}}_2$ layer.
• The substrate (back, B) contacts the bulk. Unless stated otherwise, source and back are grounded.

An $n$-bulk device is the mirror image, with $p^{+}$ islands.

Terminal conventions:

• $V_G$ is the gate voltage and $V_D$ the drain voltage, both relative to ground.
• The drain current $I_D$ is the main d.c. observable.
• Electrons always enter at the source, leave at the drain, and are controlled by the gate. That is the origin of the names.
• In normal operation the drain pn junction is reverse biased ($V_D\ge 0$ for the p-bulk device).
• For the p-bulk device $I_D$ is positive when flowing from the external circuit into the drain terminal.

Step 1: what does the gate alone do? (set $V_D=0$)

Let $V_T$ be the depletion-to-inversion transition voltage.

• If $V_G\le V_T$ (accumulation or depletion), the region between the $n^{+}$ islands holds an excess or deficit of holes and almost no electrons. Looking along the surface from source to drain you see an open circuit (two back-to-back diodes).
• If $V_G>V_T$ (inversion), a layer of mobile electrons forms at the Si surface. Looking along the surface now you see an induced “$n$-type” strip, the inversion layer or conducting channel, joining source to drain (Fig. 17.2a).

The more you invert, the more electrons pile up and the larger the channel conductance. So the gate creates the channel and sets its maximum conductance.

Step 2: what does the drain voltage do? (fix $V_G>V_T$, raise $V_D$ from 0)

Thought experiment. The channel is a thin conducting sheet lying on a hill whose height is set by the gate. The channel’s electrons exist only because the gate voltage exceeds the local channel potential. As you drive current down the channel, the channel potential rises from 0 at the source to $V_D$ at the drain. The gate’s “pull” at the drain end is therefore weaker, $V_G-V_D$ instead of $V_G$. The sheet gets thinner towards the drain.

The behavior unfolds in phases (Figs. 17.2 and 17.3):

1. $V_D=0$ (Fig. 17.2a). Thermal equilibrium, $I_D=0$.
2. Small $V_D$ (line O to A in Fig. 17.3). The channel is a plain resistor, so $I_D\propto V_D$. The reverse-biased drain junction adds a junction leakage current, but in a good device it is negligible compared with the channel current as long as $V_D$ is below junction breakdown.
3. Moderate $V_D$ (Fig. 17.2b). The voltage drop along the channel starts to cancel the gate’s inverting effect. The depletion region widens going from source to drain, and the number of inversion carriers falls. Lower carrier density means lower conductance, so the slope of the $I_D$–$V_D$ curve decreases (the curve “slopes over”).
4. Pinch-off (Fig. 17.2c, point B). The inversion layer disappears completely right at the drain end: the surface carrier concentration there falls to the bulk doping level. This onset of surface depletion at the drain end is called pinch-off. The slope of the characteristic becomes about zero. The drain voltage at which this happens is $V_{Dsat}$.
5. Post pinch-off, $V_D>V_{Dsat}$ (Fig. 17.2d). The pinched-off point grows into a depleted section of length $\Delta L$. This section has few carriers, hence low conductance, so it absorbs nearly all of the extra voltage $V_D-V_{D\text{sat}}$.

Why does the current stop growing after pinch-off? If $\Delta L\ll L$, the part of the channel from source to pinch-off point has the same shape and the same end-point voltages (0 and $V_{Dsat}$) for every $V_D\ge V_{Dsat}$. Same shape and same voltage across it means the same current. So $I_D\approx$ constant. (Water analogy: once the hose is kinked at the end, a bigger pressure just pushes the water over a “waterfall” through the kink. The flow rate is set by the pipe upstream.)

If $\Delta L$ is comparable to $L$ (short channels), the same voltage $V_{Dsat}$ drops across a shorter effective channel $L-\Delta L$, so $I_D$ creeps upward with $V_D$ after pinch-off (see the dashed part of Fig. 17.3, “channel-length modulation”).

Step 3: assembling the family of curves (Fig. 17.4)

• For $V_G\le V_T$: no channel, $I_D\approx 0$ for all $V_D$ below junction breakdown.
• For each $V_G>V_T$: a curve like Fig. 17.3. A larger $V_G$ means higher channel conductance, hence a steeper initial slope, and more carriers at pinch-off, hence a larger saturation current, achieved at a larger $V_{Dsat}$.

This is transistor action: the output-circuit current $I_D$ is modulated by the input voltage $V_G$.

Terminology.

• Saturation region: the portion of the characteristic with $V_D>V_{Dsat}$.
• Linear (triode) region: the portion with $V_D<V_{Dsat}$.
• n-channel device: channel carriers are electrons. p-channel device: channel carriers are holes.

Exercise 17.1: rewrite the section for a p-channel device

Problem. How must the figures change if the illustrative MOSFET is p-channel?

Solution (modifications).

• Fig. 17.1(a): p-type substrate becomes n-type substrate; $n^{+}$ source/drain becomes $p^{+}$ source/drain.
• Fig. 17.1(b): holes replace electrons as channel carriers; p-Si bulk becomes n-Si; $V_D\ge 0$ becomes $V_D\le 0$; arrows reversed so that positive $I_D$ flows from source to drain and out of the drain contact. (IEEE convention would make $I_D\le 0$ for a p-channel; the book prefers positive drain currents.)
• Fig. 17.2: source/drain become $p^{+}$; the inequalities in the caption flip.
• Fig. 17.3: $V_D\to -V_D$ and $V_{Dsat}\to -V_{Dsat}$ on the horizontal axis (or redraw along the negative axis).
• Fig. 17.4: ”$V_G$ increasing” becomes ”$-V_G$ increasing”, and $V_D$ becomes $-V_D$. Since $V_T<0$ for the p-channel, no current flows if $V_G>V_T$ and current flows if $V_G<V_T$.

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17.2 Quantitative $I_D$–$V_D$ Relationships

Over the history of MOSFET modeling a hierarchy of long-channel formulas appeared, each more accurate but more complex. We study two: square-law theory (simple, qualitatively right) and bulk-charge theory (accurate). All but the last derivational steps are identical.

17.2.1 Preliminary Considerations

Threshold voltage

The transistor starts to carry current (turns on) at the onset of inversion, ${\varphi }_s=2{\varphi }_F$ (here ${\varphi }_F=(kT/q)\ln (N_A/n_i)$ for p-bulk). Substituting ${\varphi }_s=2{\varphi }_F$ in the MOS-C result, Eq. (16.28), gives for an ideal device:

V_T = 2\phi_F + \frac{K_S}{K_O}\,x_o\sqrt{\frac{4qN_A\phi_F}{K_S\,\epsilon_0}} \qquad \text{ideal n-channel (p-bulk)} \tag{17.1a}

V_T = 2\phi_F - \frac{K_S}{K_O}\,x_o\sqrt{\frac{4qN_D(-\phi_F)}{K_S\,\epsilon_0}} \qquad \text{ideal p-channel (n-bulk)} \tag{17.1b}

Using $C_o=K_O{ϵ}_0/x_o$ this is $V_T=2{\varphi }_F+\sqrt{4q{K}_S{ϵ}_0{N}_A{\varphi }_F}/C_o$. Interpretation: $2{\varphi }_F$ bends the bands, and the second term pays for the depletion charge $q{N}_A{W}_{max}$ that must be supported across the oxide.

Effective mobility

In the bulk, mobility is set by lattice and ionized-impurity scattering. In a MOSFET the gate field presses the carriers against the Si–SiO${}_2$ interface (Fig. 17.5), adding surface scattering (collisions with the rough interface). The carriers closest to the surface suffer most. The average mobility of inversion-layer carriers is the effective mobility ${\bar{\mu }}_n$ (or ${\bar{\mu }}_p$).

With the geometry of Fig. 17.6 ($x$ = depth from the interface, $y$ = distance along the channel from the source, $x_c(y)$ = channel depth, $z$ = width direction with width $Z$, length $L$):

\bar\mu_n(y)=\frac{\displaystyle\int_0^{x_c(y)}\mu_n(x,y)\,n(x,y)\,dx}{\displaystyle\int_0^{x_c(y)}n(x,y)\,dx} \tag{17.2}

The channel electronic charge per cm${}^2$ at position $y$ is

Q_N(y) = -q\int_0^{x_c(y)} n(x,y)\,dx \tag{17.3}

Dividing the numerator of (17.2) by the denominator written as $-Q_N/q$ gives the alternative form

\bar\mu_n = \frac{-q}{Q_N(y)}\int_0^{x_c(y)}\mu_n(x,y)\,n(x,y)\,dx \tag{17.4}

Simplification: for long channels the $y$-dependence of ${\bar{\mu }}_n$ is small and is neglected, so ${\bar{\mu }}_n$ is taken independent of $y$ and of $V_D$.

Dependence on $V_G$: larger inversion bias means a stronger $x$-directed field, carriers squeezed closer to the interface, more surface scattering, so ${\bar{\mu }}_n$ falls with $V_G$ (Fig. 17.7). The first-order empirical model is

\bar\mu_n = \frac{\mu_0}{1+\theta\,(V_G-V_T)} \tag{17.5}

with fit constants ${\mu }_0$ and $\theta$. In Fig. 17.7: ${\mu }_{bulk}=1340$ cm${}^2$/V-s, ${\mu }_0=847$ cm${}^2$/V-s, $\theta =0.0446$ /V. The effective mobility can be far below the bulk value.

17.2.2 Square-Law Theory

Device: long-channel, Fig. 17.6. Valid for $V_G\ge V_T$ and $0\le V_D\le V_{Dsat}$.

Step 1: current density. The general electron current density is

\mathbf J_N = q\mu_n n\,\boldsymbol{\mathcal E} + qD_N\nabla n \tag{17.6}

Step 2: simplify. In the channel the current is almost entirely along $y$; diffusion of the majority-type carrier is usually negligible. So, with ${\mathcal{E}}_y=-d\varphi /dy$ ($\varphi (y)$ is the channel potential):

J_N \equiv J_{Ny} = q\mu_n n\,\mathcal E_y = -q\mu_n n\,\frac{d\phi}{dy} \tag{17.7}

(${\mu }_n$, $n$, $J_{Ny}$ all depend on $x$ and $y$; $J_{Ny}$ is large at $x=0^{+}$ and drops quickly into the bulk.)

Step 3: current continuity. Current through any cross-section equals $I_D$. Integrate $J_{Ny}$ over the channel cross-section ($Z$ wide, $x_c(y)$ deep). With $I_D$ positive in the $-y$ direction (hence the minus sign) and $d\varphi /dy$ taken constant across $x$ because the channel is thin:

I_D = -Z\int_0^{x_c(y)} J_{Ny}\,dx \tag{17.8a}

I_D = (-Z)\left(-\frac{d\phi}{dy}\right)\left(q\int_0^{x_c}\mu_n n\,dx\right) \tag{17.8b}

The last bracket equals $-{\bar{\mu }}_n{Q}_N$ by Eq. (17.4), so $I_D=(-Z)(-\frac{d\varphi }{dy})(-{\bar{\mu }}_n{Q}_N)$, i.e.

I_D = -Z\,\bar\mu_n\,Q_N(y)\,\frac{d\phi}{dy} \tag{17.9}

Sign check: $Q_N<0$ and $d\varphi /dy>0$ give $I_D>0$. Good.

Step 4: integrate along the channel. $I_D$ does not depend on $y$, and $\varphi (0)=0$, $\varphi (L)=V_D$:

\int_0^L I_D\,dy = I_DL = -Z\bar\mu_n\int_0^{V_D}Q_N\,d\phi \tag{17.10}

I_D = -\frac{Z\bar\mu_n}{L}\int_0^{V_D}Q_N\,d\phi \tag{17.11}

Step 5: charge in the channel (capacitor model). In an MOS-C above threshold, the added gate charge is balanced by the inversion charge:

\Delta Q_{gate} = -\Delta Q_{semi} = -Q_N \qquad (V_G\ge V_T) \tag{17.12}

Because the charges sit immediately against the oxide edges:

\Delta Q_{gate} \cong C_o\,\Delta V_G = C_o(V_G-V_T) \tag{17.13}

Q_N = -C_o(V_G-V_T) \qquad (V_G\ge V_T) \tag{17.14}

C_o = \frac{K_O\epsilon_0}{x_o} \tag{17.15}

In a MOSFET the “bottom plate” potential varies, from 0 at the source to $V_D$ at the drain (Fig. 17.8: a resistive-plate capacitor). The plate-to-plate potential difference is $V_G$ at the source, $V_G-V_D$ at the drain, $V_G-\varphi$ at point $y$. So the uniform drop $V_G-V_T$ is replaced by $V_G-V_T-\varphi$:

Q_N(y) = -C_o\,\big(V_G-V_T-\phi\big) \tag{17.16}

Step 6: integrate.

I_D &= \frac{Z\bar\mu_nC_o}{L}\int_0^{V_D}\big(V_G-V_T-\phi\big)\,d\phi\\ &= \frac{Z\bar\mu_nC_o}{L}\left[(V_G-V_T)\phi-\frac{\phi^2}{2}\right]_0^{V_D} \end{aligned}$$ $$\boxed{I_D = \frac{Z\bar\mu_nC_o}{L}\left[(V_G-V_T)V_D-\frac{V_D^2}{2}\right]}\qquad 0\le V_D\le V_{Dsat},\; V_G\ge V_T \tag{17.17}$$ Equation (17.17) applies **only below pinch-off**. If you plug in $V_D>V_{Dsat}$, the computed $I_D$ actually decreases. To first order, after pinch-off: $$I_D\big|_{V_D>V_{Dsat}} = I_D\big|_{V_D=V_{Dsat}}\equiv I_{Dsat} \tag{17.18}$$ so that $$I_{Dsat} = \frac{Z\bar\mu_nC_o}{L}\left[(V_G-V_T)V_{Dsat}-\frac{V_{Dsat}^2}{2}\right] \tag{17.19}$$ **Finding $V_{Dsat}$.** Pinch-off means $Q_N(L)\to0$ when $\phi(L)=V_D\to V_{Dsat}$: $$Q_N(L) = -C_o(V_G-V_T-V_{Dsat}) = 0 \tag{17.20}$$ $$V_{Dsat} = V_G-V_T \tag{17.21}$$ Substitute into (17.19): $$I_{Dsat} = \frac{Z\bar\mu_nC_o}{L}\left[(V_G-V_T)^2-\frac{(V_G-V_T)^2}{2}\right]$$ $$\boxed{I_{Dsat} = \frac{Z\bar\mu_nC_o}{2L}\,(V_G-V_T)^2} \tag{17.22}$$ This is why it is called the **square-law** theory: saturation current grows as the square of the gate overdrive (neglecting the $V_G$-dependence of $\bar\mu_n$). ### Exercise 17.2: the "universal" square-law characteristics **Problem.** Plot $I_D/(Z\bar\mu_nC_o/L)$ versus $V_D$ for $V_G-V_T=1,2,3,4$ V. Because the normalized current is $(V_G-V_T)V_D-V_D^2/2$, the plot is device independent: the same curves hold for any $Z,L,\bar\mu_n,x_o,N_A$. **Solution.** Let $V_{GT}=V_G-V_T$. Below pinch-off, normalized current $= V_{GT}V_D-V_D^2/2$ for $0\le V_D\le V_{GT}$. Above, it is constant $=V_{GT}^2/2$. Peak values are $0.5, 2, 4.5, 8$. MATLAB logic: loop over $V_{GT}$ from 4 down to 1; compute the parabola on 100 points up to $V_D=V_{GT}$ (default `linspace(0,VGT)`); append the point $V_D=9$ with the saturated value so the curve continues flat; plot with `hold on` and label each curve. ```matlab % "Universal" ID-VD Characteristics -- Square-Law Theory close clear % Let VGT = VG - VT for VGT = 4:-1:1 VD = linspace(0,VGT); % below pinch-off ID = VGT.*VD - VD.*VD./2; % ID/(Z*mu*Co/L) IDsat = VGT*VGT/2; VD = [VD, 9]; % extend flat part ID = [ID, IDsat]; if VGT == 4 plot(VD,ID); grid; axis([0 10 0 10]); xlabel('VD (volts)'); ylabel('ID/(ZCo/L)'); text(8,IDsat+0.2,'VG-VT=4V'); hold on else plot(VD,ID); if VGT == 3 text(8,IDsat+0.2,'VG-VT=3V'); elseif VGT == 2 text(8,IDsat+0.2,'VG-VT=2V'); else text(8,IDsat+0.2,'VG-VT=1V'); end end end hold off ``` (Book Fig. E17.2: four curves, each a rising parabola that flattens at $V_D=V_{GT}$; saturation heights $8, 4.5, 2, 0.5$ on a $0$–$10$ axis. The vertex of each parabola lies on the dashed locus $I=V_D^2/2$.) ### 17.2.3 Bulk-Charge Theory **The flaw in square-law theory.** The capacitor model balanced changes in gate charge only by $Q_N$. That silently assumes the depletion width stays at $W_0$ everywhere along the channel even when $V_D\neq0$. In reality (Figs. 17.2b–d) the depletion width **grows** from source to drain. This point-to-point variation of the "bulk" (depletion) charge must be included. **Step 1: charge balance with $W(y)$.** Gate charge $Q_G = C_o(V_G-V_T-\phi)+qN_AW_0$ (the threshold condition has $Q_N=0$, $W=W_0$). The semiconductor charge is $Q_N-qN_AW(y)=-Q_G$. Therefore $$Q_N(y) = -C_o\,(V_G-V_T-\phi) + qN_A\big[W(y)-W_0\big] \tag{17.23}$$ The bracket is positive (depletion widens), which **reduces** $|Q_N|$. **Step 2: depletion widths** (delta-depletion, surface potential $2\phi_F+\phi$ at point $y$): $$W(y) = \left[\frac{2K_S\epsilon_0\,(2\phi_F+\phi)}{qN_A}\right]^{1/2} \tag{17.24}$$ $$W_0 = \left[\frac{2K_S\epsilon_0\,(2\phi_F)}{qN_A}\right]^{1/2} \tag{17.25}$$ **Step 3: combine.** Define $$V_W \equiv \frac{\sqrt{4qK_S\epsilon_0N_A\phi_F}}{C_o}\qquad(\text{so } V_T=2\phi_F+V_W) \tag{17.26}$$ $$\begin{aligned} qN_A(W-W_0) &= \sqrt{2qK_S\epsilon_0N_A}\left[\sqrt{2\phi_F+\phi}-\sqrt{2\phi_F}\right]\\ &=\sqrt{4qK_S\epsilon_0N_A\phi_F}\left[\sqrt{1+\phi/2\phi_F}-1\right]\\ &=C_oV_W\left[\sqrt{1+\phi/2\phi_F}-1\right] \end{aligned}$$ Hence $$Q_N(y) = -C_o\left\{V_G-V_T-\phi-V_W\left[\sqrt{1+\frac{\phi}{2\phi_F}}-1\right]\right\} \tag{17.27}$$ **Step 4: integrate** (17.27) in (17.11): $$\begin{aligned} I_D &= \frac{Z\bar\mu_nC_o}{L}\int_0^{V_D}\left\{V_G-V_T+V_W-\phi-V_W\sqrt{1+\tfrac{\phi}{2\phi_F}}\right\}d\phi\\ &=\frac{Z\bar\mu_nC_o}{L}\left\{(V_G-V_T+V_W)V_D-\frac{V_D^2}{2}-V_W\cdot\frac{2}{3}(2\phi_F)\left[\left(1+\tfrac{V_D}{2\phi_F}\right)^{3/2}-1\right]\right\} \end{aligned}$$ using $\int\sqrt{1+\phi/2\phi_F}\,d\phi=\tfrac23(2\phi_F)(1+\phi/2\phi_F)^{3/2}$. So $$\boxed{I_D=\frac{Z\bar\mu_nC_o}{L}\left\{\Big(V_G-V_T+V_W\Big)V_D-\frac{V_D^2}{2}-\frac{4\phi_FV_W}{3}\left[\Big(1+\frac{V_D}{2\phi_F}\Big)^{3/2}-1\right]\right\}}\tag{17.28}$$ for $0\le V_D\le V_{Dsat}$, $V_G\ge V_T$. (This is algebraically equivalent to the book's printed form $\{(V_G-V_T-\tfrac{V_D}{2})V_D-\tfrac{2}{3}V_W(2\phi_F)^{1/2}\ldots\}$ rearranged. As a check, for small $V_D/2\phi_F$ expand $(1+x)^{3/2}\approx 1+\tfrac32x+\tfrac38x^2$: $I_D\approx\frac{Z\bar\mu_nC_o}{L}\{(V_G-V_T)V_D-\tfrac12(1+\tfrac{V_W}{4\phi_F})V_D^2\}$, which is the square law plus a small correction that vanishes as $V_W\to0$.) As before, post-pinch-off, $I_D\approx I_D(V_D=V_{Dsat})$. **Step 5: $V_{Dsat}$.** Set $Q_N(L)=0$ with $\phi(L)=V_{Dsat}$ in (17.27). Let $s=\sqrt{1+V_{Dsat}/2\phi_F}$, so $V_{Dsat}=2\phi_F(s^2-1)$: $$\begin{aligned} &V_G-V_T-2\phi_F(s^2-1)-V_W(s-1)=0\\ &2\phi_Fs^2+V_Ws-(V_G-V_T+V_W+2\phi_F)=0\\ &V_G-V_T+V_W+2\phi_F=V_G\quad(\text{since }V_T=2\phi_F+V_W)\\ &2\phi_Fs^2+V_Ws-V_G=0\\ &s=\frac{-V_W+\sqrt{V_W^2+8\phi_FV_G}}{4\phi_F} \end{aligned}$$ Then $V_{Dsat}=V_G-2\phi_F-V_Ws$: $$\boxed{V_{Dsat}=V_G-2\phi_F+\frac{V_W^2}{4\phi_F}-\frac{V_W}{4\phi_F}\sqrt{V_W^2+8\phi_FV_G}}\tag{17.29}$$ (Equivalently $V_{Dsat}=V_G-V_T-V_W\{[\ldots]^{1/2}-1\}$ in the book's grouping; the added term is always negative.) This is the content of Problem 17.14. **Comparing the theories (Fig. 17.9).** - Square law: simple, good for trends, qualitative reasoning, and quick algebra. - Bulk charge: agrees well with long-channel experiments. - The extra terms in (17.28) and (17.29) are **always negative**: they reduce $I_D$ and $V_{Dsat}$. - The square-law accuracy improves as substrate doping decreases. As $N_A\to0$ (and $x_o\to0$ in the sense $V_W\to0$) the bulk-charge theory reduces to the square-law theory. Fig. 17.9 used $x_o=0.1\ \mu$m, $T=300$ K, and compares $N_A=10^{14}$ and $10^{16}$ cm$^{-3}$ with the square law. ### Exercise 17.3: diode-connected MOSFET **Problem.** Gate and drain tied together. $x_o=500$ Å, $N_A=10^{16}$ cm$^{-3}$, $Z/L=10$, $\bar\mu_n=625$ cm$^2$/V-s, $T=300$ K. Using bulk-charge theory find $I_D$ for (a) $V_G=V_D=1$ V; (b) $V_G=V_D=3$ V. **Solution.** $$\phi_F=0.0259\ln\!\frac{10^{16}}{10^{10}}=0.358\ \text{V}$$ $$V_T=2\phi_F+\frac{K_S}{K_O}x_o\sqrt{\frac{4qN_A\phi_F}{K_S\epsilon_0}} =0.716+\frac{11.8}{3.9}(5\times10^{-6})\sqrt{\frac{4(1.6\times10^{-19})(10^{16})(0.358)}{(11.8)(8.85\times10^{-14})}}=1.42\ \text{V}$$ **(a)** $V_G=1\ \text{V}<V_T$, so the transistor is off: $I_D=0$. **(b)** Do **not** just put $V_D=3$ V into (17.28). In the bulk-charge theory $V_{Dsat}$ is below the square-law value $V_G-V_T$. Since $V_D=V_G>V_G-V_T>V_{Dsat}$, the device is saturated (gate tied to drain keeps it in saturation for all $V_G>V_T$). So $I_D=I_{Dsat}$. $$C_o=\frac{(3.9)(8.85\times10^{-14})}{5\times10^{-6}}=6.90\times10^{-8}\ \text{F/cm}^2$$ $$W_0=\left[\frac{2K_S\epsilon_0(2\phi_F)}{qN_A}\right]^{1/2}=3.06\times10^{-5}\ \text{cm}$$ $$V_W=\frac{qN_AW_0}{C_o}=0.71\ \text{V}$$ From (17.29) with $V_G=3$ V: $V_{Dsat}\approx1.15$ V. Then, from (17.28) at $V_D=V_{Dsat}$: $$\frac{Z\bar\mu_nC_o}{L}=10(625)(6.90\times10^{-8})=4.31\times10^{-4}\ \text{A/V}^2$$ $$\{\ldots\}\approx0.885\ \text{V}^2\quad\Rightarrow\quad I_D\approx 0.382\ \text{mA}$$ (The braces: $1.80-0.65+0.81-1.08\approx0.89$ with $V_D=1.14$ V.) ### 17.2.4 Charge-Sheet and Exact-Charge Theories Both earlier theories have two built-in limitations: 1. $Q_N$ is taken as **exactly zero** at and below $V_T$. In a real device the channel charge becomes small but never vanishes, so a residual **subthreshold current** flows. Its value is often important (leakage, low-power circuits). 2. They do **not self-saturate**: the post-pinch-off part must be added by hand. The **charge-sheet** and **exact-charge** theories remove both flaws: either can compute the subthreshold current and both saturate by themselves. (Their computational formulas are in Appendix D, which is outside this slice. Section "Problem 17.16" below uses the standard equivalent formulation.) The exact-charge result uses the exact charge distribution and involves integrals; the charge-sheet model is a simplified version (all inversion charge assumed to sit in an infinitely thin sheet at the surface) and offers the best accuracy/complexity trade-off. Figures 17.10 and 17.11 show: (i) theoretical $I_D$–$V_D$ curves for an n-channel device with $x_o=0.05\ \mu$m, $N_A=10^{15}$ cm$^{-3}$, $\bar\mu_n=550$, $L=7\ \mu$m, $Z=70\ \mu$m, $T=23^\circ$C, $V_G=2,3,4,5$ V (solid exact-charge, dashed charge-sheet, nearly coincident); (ii) subthreshold transfer characteristics, $\log I_D$ versus $V_G$ at $V_D=1$ V, for $N_A=10^{14}$ and $10^{15}$ cm$^{-3}$, with $I_D$ falling roughly exponentially from about $10^{-4}$–$10^{-5}$ A down to $10^{-10}$ A as $V_G$ goes from about $+0.4$ V to $-0.6$ V, and experimental points following the theory. --- ## 17.3 a.c. Response ### 17.3.1 Small-Signal Equivalent Circuits View the MOSFET as a **two-port** (Fig. 17.12a): input between gate and source, output between drain and source (source common). First restrict attention to **low frequencies**, where capacitive effects are negligible. (This mirrors the J-FET treatment of Subsection 15.2.4.) **Input port.** Looking into the gate you see a capacitor. A capacitor is an open circuit at low frequency, so the low-frequency input is modeled by an **open circuit**. **Output port.** The d.c. current is a function $I_D=I_D(V_D,V_G)$. Add small a.c. voltages $v_d$ and $v_g$ to the d.c. biases. If the device can follow (low frequency): $$I_D+i_d=I_D(V_D+v_d,\;V_G+v_g) \tag{17.30a}$$ $$i_d=I_D(V_D+v_d,\;V_G+v_g)-I_D(V_D,V_G) \tag{17.30b}$$ Taylor-expand about the d.c. operating point and keep first-order terms: $$I_D(V_D+v_d,V_G+v_g)=I_D(V_D,V_G)+\left.\frac{\partial I_D}{\partial V_D}\right|_{V_G}v_d+\left.\frac{\partial I_D}{\partial V_G}\right|_{V_D}v_g \tag{17.31}$$ Substitute into (17.30b): $$i_d=\left.\frac{\partial I_D}{\partial V_D}\right|_{V_G}v_d+\left.\frac{\partial I_D}{\partial V_G}\right|_{V_D}v_g \tag{17.32}$$ The partial derivatives have dimensions of conductance. Define $$g_d\equiv\left.\frac{\partial I_D}{\partial V_D}\right|_{V_G=\text{const}}\quad\text{(drain or channel conductance)}\tag{17.33a}$$ $$g_m\equiv\left.\frac{\partial I_D}{\partial V_G}\right|_{V_D=\text{const}}\quad\text{(transconductance or mutual conductance)}\tag{17.33b}$$ $$i_d=g_dv_d+g_mv_g \tag{17.34}$$ Equation (17.34) is the a.c. current-node equation at the drain: a conductance $g_d$ from drain to source in parallel with a current source $g_mv_g$ (Fig. 17.12b). Together with the open-circuit input, this is the **low-frequency small-signal equivalent circuit**. For FETs, $g_m$ plays the role that $\alpha$ and $\beta$ play for BJTs. Explicit $g_d$, $g_m$ come from differentiating (17.17), (17.22), (17.28) per the definitions (17.33). Write $\xi=Z\bar\mu_nC_o/L$ (the $V_G$-dependence of $\bar\mu_n$ is neglected). **Table 17.1 MOSFET small-signal parameters** | | Below pinch-off ($V_D\le V_{Dsat}$) | Above pinch-off ($V_D>V_{Dsat}$) | |---|---|---| | Square law $g_d$ | $\xi\,(V_G-V_T-V_D)$ | $0$ | | Square law $g_m$ | $\xi\,V_D$ | $\xi\,(V_G-V_T)$ | | Bulk charge $g_d$ | $\xi\left[V_G-V_T-V_D+V_W\left(1-\sqrt{1+V_D/2\phi_F}\right)\right]$ | $0$ | | Bulk charge $g_m$ | $\xi\,V_D$ | $\xi\,V_{Dsat}$, with $V_{Dsat}$ from (17.29) | (The bulk-charge below-pinch-off $g_d$ equals $-Z\bar\mu_nQ_N(L)/L$, the channel charge at the drain end. Each entry is verified in Problem 17.17.) **High frequencies.** The circuit must include capacitive coupling between terminals (Fig. 17.12c). A drain-to-source capacitor is omitted because it is usually negligible. Two capacitors appear: - $C_{gd}$: the **overlap capacitance**, from the part of the gate overlapping the drain island. It is minimized with a thicker oxide at the overlap, or better with **self-aligned gate** processing: poly-Si is deposited first, the gate defined, then source and drain islands formed by diffusion or implantation abutting the gate edges. - $C_{gs}$: essentially the capacitance of the MOS gate, $C_{gs}\approx C_G$. ### 17.3.2 Cutoff Frequency Define $\omega_{max}$ ($f_{max}$) as the frequency where the output-to-input current ratio, with the output **short-circuited**, has magnitude one: the transistor no longer amplifies. With $C_{gd}$ small and $C_{gs}\approx C_G$ ($=C_oZL$): $$i_{in}=j\omega\,(C_{gs}+C_{gd})\,v_g\approx j(2\pi f)\,C_G\,v_g\qquad(j=\sqrt{-1}) \tag{17.35}$$ $$i_{out}=g_mv_g \tag{17.36}$$ Setting $|i_{out}/i_{in}|=1$: $$\frac{g_m}{2\pi f_{max}C_G}=1\;\Rightarrow\; f_{max}=\frac{g_m}{2\pi C_G}$$ Using $g_m=\xi V_D$ (below pinch-off) and $C_G=C_oZL$: $$f_{max}=\frac{\bar\mu_nV_D}{2\pi L^2}\qquad(V_D\le V_{Dsat}) \tag{17.37}$$ The key message: **channel length $L$** controls $f_{max}$, and it enters squared. Shrinking $L$ is the route to fast transistors. (Intuition: $f_{max}\sim1/\text{transit time}$, and the transit time is $L/v=L^2/(\mu V_D)$.) ### 17.3.3 Small-Signal Characteristics Fig. 17.13 shows two typical characteristics. **(a) $g_d$ versus $V_G$ at $V_D=0$.** At $V_D=0$ both theories give $$g_d=\frac{Z\bar\mu_nC_o}{L}\,(V_G-V_T)\qquad(V_D=0) \tag{17.38}$$ This is linear in $V_G$ and goes to zero at $V_G=V_T$. So extrapolating the linear part of $g_d$–$V_G$ to the $V_G$ axis gives an accurate estimate of $V_T$. The measured curve does not vanish sharply at $V_T$ because a small minority-carrier concentration exists at the transition, which the theory neglects. Since $g_d\propto\bar\mu_n$, the same data give $\bar\mu_n$ versus $V_G$ directly. This works well if the interface-trap density is low. A moderate-to-large trap density smears the $g_d$–$V_G$ curve and yields a falsely low $\bar\mu_n$ (see Subsection 18.2.4). **(b) Gate capacitance $C_G$ versus $V_G$ at $V_D=0$** (drain grounded). It is used for diagnostics just like the MOS-C $C$–$V$ curve and can be modeled to first order by the **low-frequency** MOS-C curve, even when probed above 1 MHz. Why? The source and drain islands supply the minority carriers. Electrons just run laterally through the surface channel into and out of the gate area to follow the a.c. signal. In the MOS-C, minorities must be thermally generated and are too slow. The curve goes from $C_{Gmax}=C_oZL$ in accumulation, dips to a minimum in depletion, and returns to $C_{Gmax}$ in inversion. ### Exercise 17.4: $g_m$–$V_G$ characteristics **Problem.** (a) Deduce the general form of $g_m$ versus $V_G$ with $V_D$ fixed. Using the square-law entries and $V_T=2$ V, plot $g_m/(Z\bar\mu_nC_o/L)$ versus $V_G$ ($0\le V_G\le10$ V) for $V_D=2,4,6$ V, neglecting $\bar\mu_n(V_G)$. (b) Compare with experimental curves and speculate on differences. **Solution (a).** With $\xi=Z\bar\mu_nC_o/L$, Table 17.1 gives $$\frac{g_m}{\xi}=\begin{cases}0 & V_G<V_T\\ V_G-V_T & 0\le V_G-V_T\le V_D\ \text{(saturated)}\\ V_D & V_G-V_T\ge V_D\ \text{(below pinch-off)}\end{cases}$$ For each $V_D$: zero until $V_G=V_T=2$ V; then it rises linearly with slope 1; at $V_G=2+V_D$ the device leaves saturation and $g_m/\xi$ stays flat at $V_D$. Plateaus of 2, 4, 6 are reached at $V_G=4,6,8$ V. ```matlab VT = 2; VG = linspace(0,10,501); hold on for VD = [2 4 6] gm = zeros(size(VG)); sat = (VG>VT) & (VG-VT<=VD); % saturation: gm/xi = VG-VT lin = (VG-VT>VD); % below pinch-off: gm/xi = VD gm(sat) = VG(sat)-VT; gm(lin) = VD; plot(VG,gm); text(10.1,VD,['VD=' num2str(VD) 'V']); end xlabel('VG (volts)'); ylabel('gm/(Z mu Co/L)'); grid; hold off ``` **(b)** Experimental $g_m$ ($V_D$ from 2 to 6 V, $g_m$ up to about 2.5 mS) shows the same rise but **falls off** for $V_G>V_D+V_T$ instead of staying flat. The cause is the decrease of $\bar\mu_n$ with $V_G$ (surface scattering, Eq. 17.5), which the theory neglected. --- ## 17.4 Summary The chapter introduced MOSFET terminology, operation and analysis for an ideal MOS structure and the basic transistor. - **Qualitative picture.** Inversion creates a surface channel between source and drain. The larger the gate voltage above turn-on, the more conductive the channel at a given $V_D$. A nonzero $V_D$ drives current: proportional to $V_D$ at small $V_D$, sloping over as the channel narrows, and **saturating** when the channel pinches off near the drain. - **Two complications in the quantitative analysis.** (1) Surface scattering reduces mobility, requiring an **effective mobility**. (2) The carrier concentration and current density in the channel vary strongly with position and drop rapidly into the bulk. Even so, the first-order result is surprisingly simple. - **Square-law theory:** Eqs. (17.17), (17.21), (17.22). **Bulk-charge theory** (more accurate, more complex): Eqs. (17.28), (17.29). More exacting theories (charge-sheet, exact-charge) are in Appendix D. - **a.c. response.** Low- and high-frequency small-signal circuits (Figs. 17.12b, c). A **short channel** is required for high-frequency operation, since $f_{max}\propto1/L^2$. Useful information (threshold voltage, effective mobility, interface quality) is extracted from $g_d$, $g_m$, $C_G$ versus d.c. bias. - The treatment parallels the J-FET of Chapter 15; comparing the two is a worthwhile exercise (Problem 17.22). Chapter 18 treats nonidealities; Chapter 19 small-dimension effects and structural variations. --- # Chapter 17 Problems The book's **Problem Information Table** classifies the problems as follows (difficulty level 1 to 4): | Problem | After section | Level | Points | Description | |---|---|---|---|---| | 17.1 | 17.4 | 1 | 10 | Quick quiz | | 17.2 | 17.4 | 2 | 10 | Sample computations | | 17.3 | 17.1 | 2 | 10 | Sketch diagrams | | 17.4 | 17.2.1 | 2 | 10 | Plot $V_T$ vs. $N_A$ for select $x_o$ | | 17.5 | 17.2.1 | 3 | 10 | $V_T$ temperature dependence | | 17.6 | 17.2.2 | 2 | 5 | $V_{Dsat}$ from $I_D$ maximum | | 17.7 | 17.2.2 | 2–3 | 10 | n to p in Subsection 17.2.2 | | 17.8 | 17.2.2 | 1 | 5 | Plot $I_D$–$V_D$, $\bar\mu_n$ per Eq. (17.5) | | 17.9 | 17.2.2 | 3 | 10 | $V_D=V_G-V_B$ | | 17.10 | 17.2.2 | 3–4 | 10 | $I_D$ versus $V_G-V_T$ | | 17.11 | 17.2.2 | 3–4 | 10 | Circular MOSFET | | 17.12 | 17.2.2 | 3 | 12 | $I_D$ temperature dependence | | 17.13 | 17.2.2 | 3–4 | 12 | Include $R_S$, $R_D$ in theory | | 17.14 | 17.2.3 | 3–4 | 10 | Derive Eq. (17.29) | | 17.15 | 17.2.3 | 3 | 10 | Plot bulk-charge $I_D$–$V_D$ | | 17.16 | 17.2.4 | 4 | 25 | Plot sheet, exact $I_D$–$V_D$ | | 17.17 | 17.3.1 | 2 | 5 | Verify Table 17.1 entries | | 17.18 | 17.3.1 | 2 | 5 | MOSFET $Q_N$, $g_d$ | | 17.19 | 17.3.2 | 3 | 10 | Deduce $Z$, $L$ for match | | 17.20 | 17.3.2 | 2–3 | 15 | General MOSFET review | | 17.21 | 17.3.3 | 3 | 12 | Small-signal characteristics | | 17.22 | 17.4 | 2 | 12 | Compare FETs | Constants used below unless stated: $T=300$ K, $kT/q=0.0259$ V, $n_i=10^{10}$ cm$^{-3}$, $K_S=11.8$, $K_O=3.9$, $\epsilon_0=8.85\times10^{-14}$ F/cm, $q=1.6\times10^{-19}$ C. Write $\xi\equiv Z\bar\mu_nC_o/L$. ## Problem 17.1: Quick quiz **(a) Why are the current-carrying contacts called source and drain?** Carriers (electrons in an n-channel device) enter the structure through the **source** (the origin of the carriers) and leave through the **drain** (where they are drained out of the channel). **(b) What is the channel?** The channel is the **surface inversion layer** induced by the gate between the source and drain islands: a thin conducting sheet of mobile carriers (electrons in an n-channel device, holes in a p-channel device). **(c) What is the saturation region?** It is the part of the $I_D$–$V_D$ characteristic with $V_D>V_{Dsat}$, i.e. beyond pinch-off, where $I_D$ is (nearly) independent of $V_D$. **(d) Difference between the depletion-inversion transition voltage and the threshold voltage?** (The item is cut off in the OCR; it asks to compare the "inversion point voltage" of the MOS-C discussion with the MOSFET threshold.) In an ideal device they are the **same quantity**: $V_T$ is the gate voltage at which $\phi_s=2\phi_F$. In the MOS-C it marks the onset of inversion; in the MOSFET it is called the turn-on voltage because the channel (conducting path) first appears there. **(e) Why is the surface-channel mobility different from the bulk mobility?** Besides lattice and ionized-impurity scattering, channel carriers are pressed against the Si–SiO$_2$ interface by the gate field and suffer **surface scattering**. Hence $\bar\mu_n<\mu_n^{bulk}$. **(f) Why "square-law" theory?** Because the saturation current is proportional to the **square** of the gate overdrive, $I_{Dsat}=\frac{Z\bar\mu_nC_o}{2L}(V_G-V_T)^2$ (and $I_D$ involves $V_D^2$ below pinch-off). **(g) Why "bulk-charge" theory?** Because the point-to-point variation of the **depletion ("bulk") charge** along the channel, $qN_A[W(y)-W_0]$, is included in the charge balance (Eq. 17.23). **(h) What is plotted in the subthreshold transfer characteristics?** $\log I_D$ (vertical axis) versus $V_G$ (horizontal), with $V_D$ held constant. **(i) Definitions of $g_d$ and $g_m$.** $$g_d=\left.\frac{\partial I_D}{\partial V_D}\right|_{V_G},\qquad g_m=\left.\frac{\partial I_D}{\partial V_G}\right|_{V_D}$$ **(j) Why is the measured $C$–$V_G$ ($V_D=0$) a low-frequency curve even at 1 MHz?** The source/drain islands directly supply the minority carriers needed to follow the a.c. signal; they flow laterally through the channel, so no slow generation process is involved. ## Problem 17.2: Sample calculations **Problem.** Ideal n-channel MOSFET, $T=300$ K, $Z=50\ \mu$m, $L=5\ \mu$m, $x_o=0.05\ \mu$m, $N_A=10^{16}$ cm$^{-3}$, $\bar\mu_n=800$ cm$^2$/V-s (independent of $V_G$). Find: (a) $V_T$; (b) $I_{Dsat}$ (square law) if $V_G-V_T=2$ V; (c) $I_{Dsat}$ (bulk charge) if $V_G-V_T=2$ V; (d) $g_d$ if $V_G-V_T=2$ V, $V_D=0$; (e) $g_m$ (square law) if $V_G-V_T=2$ V, $V_D=2$ V; (f) $g_m$ (bulk charge), same bias; (g) $f_{max}$ if $V_G-V_T=2$ V, $V_D=1$ V. **Solution.** Common quantities: $$\phi_F=0.0259\ln\frac{10^{16}}{10^{10}}=0.358\ \text{V}$$ $$C_o=\frac{K_O\epsilon_0}{x_o}=\frac{(3.9)(8.85\times10^{-14})}{5\times10^{-6}}=6.90\times10^{-8}\ \text{F/cm}^2$$ $$\xi=\frac{Z}{L}\bar\mu_nC_o=(10)(800)(6.90\times10^{-8})=5.52\times10^{-4}\ \text{A/V}^2$$ **(a)** $$V_W=\frac{\sqrt{4qK_S\epsilon_0N_A\phi_F}}{C_o}=\frac{\sqrt{4(1.6\times10^{-19})(11.8)(8.85\times10^{-14})(10^{16})(0.358)}}{6.90\times10^{-8}}$$ Numerator: $\sqrt{2.39\times10^{-15}}\approx4.88\times10^{-8}$ C/cm$^2$, so $V_W=0.708$ V. $$V_T=2\phi_F+V_W=0.716+0.708=1.42\ \text{V}$$ **(b)** Square law, (17.22): $$I_{Dsat}=\frac{\xi}{2}(V_G-V_T)^2=\frac{5.52\times10^{-4}}{2}(2)^2=1.10\ \text{mA}$$ **(c)** Bulk charge: $V_G=V_T+2=3.42$ V. From (17.29): $$\sqrt{V_W^2+8\phi_FV_G}=\sqrt{0.501+9.795}=3.209$$ $$s=\frac{-0.708+3.209}{4(0.358)}=1.747\ ;\quad V_{Dsat}=V_G-2\phi_F-V_Ws=3.42-0.716-1.237=1.47\ \text{V}$$ From (17.28) at $V_D=1.47$ V: $$\{\ldots\}=(2+0.708)(1.47)-\frac{(1.47)^2}{2}-\frac{4(0.358)(0.708)}{3}\left[\left(1+\frac{1.47}{0.716}\right)^{3/2}-1\right]$$ $$=3.981-1.080-0.338\,(5.34-1)\;\Rightarrow\;\{\ldots\}\approx1.435\ \text{V}^2$$ $$I_{Dsat}=\xi(1.435)=0.79\ \text{mA}$$ (The bulk-charge value is about 28% below the square-law value.) **(d)** At $V_D=0$ (Table 17.1 or (17.38)): $$g_d=\xi(V_G-V_T)=(5.52\times10^{-4})(2)=1.10\ \text{mS}$$ **(e)** Square law: $V_{Dsat}=V_G-V_T=2$ V $=V_D$, so the device sits at the pinch-off edge; both below- and above-pinch-off formulas agree: $$g_m=\xi V_D=(5.52\times10^{-4})(2)=1.10\ \text{mS}$$ **(f)** Bulk charge: $V_{Dsat}=1.47$ V $<V_D=2$ V, so the device is saturated, and $g_m=\xi V_{Dsat}$: $$g_m=(5.52\times10^{-4})(1.47)=0.81\ \text{mS}$$ **(g)** Below pinch-off ($V_D=1$ V $<V_{Dsat}$ in either theory): $$f_{max}=\frac{\bar\mu_nV_D}{2\pi L^2}=\frac{(800)(1)}{2\pi(5\times10^{-4})^2}=\frac{800}{1.571\times10^{-6}}=5.1\times10^{8}\ \text{Hz}\approx509\ \text{MHz}$$ ## Problem 17.3: Sketches for an ideal p-channel MOSFET **(a) Energy-band diagram at threshold, $V_D=0$ (n-bulk, p-channel).** Here $\phi_F<0$ ($E_F$ above $E_i$ in the bulk) and threshold is $V_G=V_T<0$. - Far from the surface: $E_F$ lies $q|\phi_F|$ **above** $E_i$. - Toward the surface the bands bend **upward** by $2q|\phi_F|$, so at the interface $E_i$ lies $q|\phi_F|$ **above** $E_F$ (the surface is as p-type as the bulk is n-type: inversion onset). A depletion region of width $W_{max}$ spans the bend. - Oxide: bands slope across it (a linear potential drop $V_{ox}$), with the gate Fermi level $E_{FM}$ **above** $E_F$ by $q|V_T|$ because $V_G<0$. - Ideal structure: no flat-band offset, so at $V_G=0$ everything would be flat. **(b) Block charge diagram at threshold.** - Gate: charge per unit area $-qN_DW_{max}$ (negative sheet at the gate/oxide interface; a block drawn below the axis at the oxide edge). - Semiconductor: a block of height $+qN_D$ and width $W_{max}$ (ionized donors, positive, depletion) starting at the oxide-semiconductor interface. Inversion charge is zero at threshold. - Total charge is zero: $-qN_DW_{max}+qN_DW_{max}=0$. **(c) Inversion layer and depletion region at pinch-off.** Draw a p-channel device: n-type substrate, $p^+$ source on the left and $p^+$ drain on the right, oxide and gate above, $V_D<0$. The hole inversion layer is a thin strip under the oxide, thick at the source and tapering to zero thickness exactly at the drain edge. Beneath it the n-type depletion region has constant width at the source and widens toward the drain, merging with the drain-substrate junction depletion region. Label: gate, oxide, $p^+$ source/drain, n-substrate, inversion layer, depletion region, channel length $L$, pinch-off point at the drain end ($\Delta L=0$). ## Problem 17.4: $V_T$ versus $N_A$ **Problem.** Plot $V_T$ vs. $N_A$ for ideal n-channel MOSFETs at room temperature, with curves for $x_o=0.0,0.02,0.05,0.1\ \mu$m, $10^{14}\le N_A\le10^{18}$ cm$^{-3}$, plotted $V_T$ limited to 0 to 3 V. **Solution.** Use (17.1a): $V_T=2\phi_F+\sqrt{4qK_S\epsilon_0N_A\phi_F}\,x_o/(K_O\epsilon_0)$, with $\phi_F=(kT/q)\ln(N_A/n_i)$. For $x_o=0$ the second term vanishes: $V_T=2\phi_F$ (only the band bending term). For finite $x_o$ the curve lies above it and rises faster with $N_A$ (the depletion charge $\propto\sqrt{N_A}$ is paid across the oxide). ```matlab % VT versus NA for ideal n-channel MOSFETs close; clear q = 1.6e-19; e0 = 8.85e-14; Ks = 11.8; Ko = 3.9; kT = 0.0259; ni = 1e10; NA = logspace(14,18,200); % cm^-3 phiF = kT*log(NA/ni); xo_list = [0.0 0.02 0.05 0.1]*1e-4; % um -> cm for xo = xo_list Co = Ko*e0/max(xo,eps); % F/cm^2 (xo=0: second term set to 0) if xo == 0, VT = 2*phiF; else, VT = 2*phiF + sqrt(4*q*Ks*e0*NA.*phiF)/Co; end semilogx(NA,VT); hold on end axis([1e14 1e18 0 3]); grid xlabel('N_A (cm^{-3})'); ylabel('V_T (volts)'); legend('x_o=0','0.02 \mum','0.05 \mum','0.1 \mum','Location','NorthWest'); hold off ``` Representative values (computed): at $N_A=10^{16}$: $V_T=0.72$ V ($x_o=0$), $1.00$ V (0.02 $\mu$m), $1.42$ V (0.05 $\mu$m), $2.13$ V (0.1 $\mu$m). The $x_o=0$ curve runs from about $0.48$ V at $10^{14}$ to $0.95$ V at $10^{18}$; thick-oxide curves leave the plotted window ($V_T>3$ V) at high $N_A$. ## Problem 17.5: Temperature dependence of $V_T$ **Problem.** Ideal n-channel MOSFET, $x_o$ and $N_A$ inputs. Write a program to plot $V_T$ vs. $T$, $200\le T\le400$ K. Record the output for $x_o=0.1\ \mu$m and $N_A=10^{16}$ cm$^{-3}$ (the OCR shows "$10^6$"; $10^{16}$ is the intended value). Describe the dependence. **Solution (logic).** $T$ enters through $kT/q$ and through $n_i(T)$ inside $\phi_F$: $$\phi_F(T)=\frac{kT}{q}\ln\frac{N_A}{n_i(T)},\qquad n_i(T)=n_i(300)\left(\frac{T}{300}\right)^{3/2}\exp\!\left[-\frac{E_G}{2k}\left(\frac1T-\frac1{300}\right)\right]$$ **Assumptions:** $E_G=1.12$ eV independent of $T$, $n_i(300)=10^{10}$ cm$^{-3}$ (Exercise 2.4 style). The depletion term also depends on $T$ through $\phi_F$. Then use (17.1a). ```matlab % VT versus temperature, ideal n-channel MOSFET close; clear q = 1.6e-19; e0 = 8.85e-14; Ks = 11.8; Ko = 3.9; k = 8.617e-5; % eV/K xo = input('xo in um = ')*1e-4; NA = input('NA in cm^-3 = '); Co = Ko*e0/xo; Eg = 1.12; T = 200:5:400; ni = 1e10*(T/300).^1.5.*exp(-(Eg/(2*k))*(1./T-1/300)); phiF = k*T.*log(NA./ni); % kT/q in volts = k*T VT = 2*phiF + sqrt(4*q*Ks*e0*NA*phiF)/Co; plot(T,VT); grid; xlabel('T (K)'); ylabel('V_T (volts)'); disp([T(1:10:end)' VT(1:10:end)']) ``` Output for $x_o=0.1\ \mu$m, $N_A=10^{16}$ cm$^{-3}$ (computed with the assumptions above): | $T$ (K) | 200 | 250 | 300 | 350 | 400 | |---|---|---|---|---|---| | $V_T$ (V) | 2.43 | 2.29 | 2.13 | 1.96 | 1.79 | **Description.** $V_T$ **decreases almost linearly** with temperature, about $-3.2$ mV/K (a total drop of roughly 0.64 V over 200 K). Reason: as $T$ rises, $n_i$ rises sharply, the Fermi level moves toward midgap, $\phi_F$ decreases, and both terms of $V_T$ shrink. ## Problem 17.6: $V_{Dsat}$ from the $I_D$ maximum **Problem.** If (17.17) is used beyond $V_{Dsat}$, $I_D$ peaks at $V_{Dsat}$. Use this to derive (17.21) from (17.17). **Solution.** A maximum requires $\partial I_D/\partial V_D=0$ with $\partial^2I_D/\partial V_D^2<0$. $$\frac{\partial I_D}{\partial V_D}=\xi\left[(V_G-V_T)-V_D\right]=0$$ $$V_D=V_G-V_T\equiv V_{Dsat}$$ $$\frac{\partial^2I_D}{\partial V_D^2}=-\xi<0\quad(\text{a maximum, as required})$$ This reproduces (17.21). (Physically the derivative $g_d=\xi(V_G-V_T-V_D)=-Z\bar\mu_nQ_N(L)/L$ vanishes exactly when the channel charge at the drain end vanishes.) ## Problem 17.7: Subsection 17.2.2 for a p-channel device **Problem.** Indicate how the equations of Subsection 17.2.2 change for a p-channel MOSFET. **Solution.** Setup: n-bulk, holes in the channel, $V_G<V_T<0$, $V_D\le0$, source grounded, $\phi(0)=0$, $\phi(L)=V_D$, $\phi\le0$. $I_D$ is taken positive for holes flowing from source to drain. Step by step: $$J_P=q\mu_pp\,\mathcal E-qD_P\nabla p\;\to\; J_{Py}=q\mu_pp\,\mathcal E_y=-q\mu_pp\,\frac{d\phi}{dy}\qquad(17.7\text{ with }\mu_n\to\mu_p,\ n\to p)$$ $$Q_P(y)=+q\int_0^{x_c}p\,dx>0\qquad(17.3)$$ $$I_D=Z\int_0^{x_c}J_{Py}\,dx=-Z\bar\mu_pQ_P\frac{d\phi}{dy}\qquad(17.9)$$ $$I_DL=-Z\bar\mu_p\int_0^{V_D}Q_P\,d\phi\qquad(17.10,\,17.11)$$ Charge: for $V_G\le V_T$, the added gate charge is negative and balanced by $+Q_P$: $$Q_P=-C_o(V_G-V_T)\qquad(17.14),\qquad Q_P(y)=-C_o(V_G-V_T-\phi)\qquad(17.16)$$ This is positive since $V_G-V_T-\phi<0$. Integrate: $$I_D=\frac{Z\bar\mu_pC_o}{L}\int_0^{V_D}(V_G-V_T-\phi)\,d\phi$$ $$I_D=\frac{Z\bar\mu_pC_o}{L}\left[(V_G-V_T)V_D-\frac{V_D^2}{2}\right]\qquad(V_D\ge V_{Dsat},\ V_G\le V_T)\qquad(17.17)$$ Both terms keep the same form, but note the sign bookkeeping: $(V_G-V_T)V_D>0$ since both factors are negative, and the inequality on $V_D$ reverses ($|V_D|\le|V_{Dsat}|$). Pinch-off ($Q_P(L)=0$): $$V_{Dsat}=V_G-V_T\ (<0)\qquad(17.21)$$ $$I_{Dsat}=\frac{Z\bar\mu_pC_o}{2L}(V_G-V_T)^2\qquad(17.22)$$ Also: $V_T$ per (17.1b), $\bar\mu_n\to\bar\mu_p$ everywhere, and "$V_G\ge V_T$" becomes "$V_G\le V_T$", "$0\le V_D\le V_{Dsat}$" becomes "$V_{Dsat}\le V_D\le0$". ## Problem 17.8: Effect of $\bar\mu_n(V_G)$ **Problem.** Modify the Exercise 17.2 program, replacing $\bar\mu_n$ with Eq. (17.5). Normalize by $Z\mu_0C_o/L$ and superimpose plots for $\theta=0$ and $\theta=0.05$/V. **Solution.** With $\bar\mu_n=\mu_0/[1+\theta(V_G-V_T)]$: $$\frac{I_D}{Z\mu_0C_o/L}=\frac{V_{GT}V_D-V_D^2/2}{1+\theta V_{GT}}\ (V_D\le V_{GT}),\qquad\frac{I_{Dsat}}{Z\mu_0C_o/L}=\frac{V_{GT}^2/2}{1+\theta V_{GT}}$$ For $\theta=0.05$/V the saturation heights become $0.5/1.05=0.476$, $2/1.1=1.82$, $4.5/1.15=3.91$, $8/1.2=6.67$ (instead of $0.5,2,4.5,8$). The curves are progressively compressed at high $V_{GT}$, spacing between curves shrinks (the $V_G$ dependence becomes closer to linear than quadratic). ```matlab close; clear styles = {'-','--'}; theta_list = [0 0.05]; for it = 1:2 theta = theta_list(it); for VGT = 4:-1:1 VD = linspace(0,VGT); ID = (VGT.*VD - VD.*VD./2)/(1+theta*VGT); IDsat = VGT*VGT/2/(1+theta*VGT); VD = [VD, 9]; ID = [ID, IDsat]; plot(VD,ID,styles{it}); hold on end end grid; axis([0 10 0 10]); xlabel('VD (volts)'); ylabel('ID/(Z mu_0 Co/L)'); legend('\theta=0'); hold off % solid: theta=0, dashed: theta=0.05/V ``` ## Problem 17.9: Gate-drain battery **Problem.** A battery $V_B\ge0$ between gate and drain gives $V_D=V_G-V_B$, i.e. $V_G=V_D+V_B$. Using the square-law results, sketch $I_D$ vs. $V_D$ ($V_D\ge0$) for (a) $V_B=V_T/2$; (b) $V_B=2V_T$. **Solution.** The gate overdrive is $V_G-V_T=V_D+V_B-V_T$. Pinch-off condition: $V_D\ge V_G-V_T$, i.e. $V_D\ge V_D+V_B-V_T$, i.e. $V_B\le V_T$. **(a) $V_B=V_T/2\ (<V_T)$.** The pinch-off condition is satisfied for every $V_D$ at which the device is on, so it is always in saturation. It is on when $V_G\ge V_T$: $V_D\ge V_T/2$. $$I_D=\begin{cases}0 & V_D<V_T/2\\[2pt] \dfrac{\xi}{2}\left(V_D-\dfrac{V_T}{2}\right)^2 & V_D\ge V_T/2\end{cases}$$ Sketch: zero out to $V_D=V_T/2$, then a parabola starting with zero slope and growing quadratically (a diode-like "knee"). **(b) $V_B=2V_T\ (>V_T)$.** The device is on already at $V_D=0$ ($V_G=2V_T$), and the pinch-off condition $V_B\le V_T$ is never satisfied, so it stays in the linear region: $$I_D=\xi\left[(V_D+V_T)V_D-\frac{V_D^2}{2}\right]=\xi\left[V_TV_D+\frac{V_D^2}{2}\right]$$ Sketch: starts at the origin with slope $\xi V_T$, then curves **upward** (concave up) as the gate rises together with the drain. (This is the physical consequence of increasing both together.) ## Problem 17.10: $I_D$ versus $V_G-V_T$ at constant $V_D$ **Problem.** Sketch $I_D$ versus $V_G-V_T$ for $V_D=1,2,3,4$ V (the OCR reads "$,2,3,$ and 4 V"; 1 V is the missing value) and explain. **Solution.** Let $x=V_G-V_T$. For $x<0$: $I_D=0$. For $0\le x\le V_D$ the device is **saturated** (since $V_D\ge x=V_{Dsat}$): $$I_D=\frac{\xi}{2}x^2$$ For $x\ge V_D$ the device is **below pinch-off**: $$I_D=\xi\left(xV_D-\frac{V_D^2}{2}\right)$$ This is a straight line with slope $\xi V_D$. At $x=V_D$ both give $\xi V_D^2/2$, and the slopes agree ($\xi x=\xi V_D$): the line is **tangent** to the parabola. So each curve is zero until $x=0$, follows the common parabola $\xi x^2/2$ up to $x=V_D$, and then continues as a straight line of slope $\xi V_D$ (steeper for larger $V_D$). The line extrapolates back to the $x$-axis at $x=V_D/2$. All four curves share the same parabola and peel off it at $x=1,2,3,4$ V. ## Problem 17.11: Circular MOSFET **Problem.** Gate is an annulus (Fig. P17.11). With $r_1,r_2$ the inside and outside radii, show $I_D=\dfrac{2\pi\bar\mu_nC_o}{\ln(r_2/r_1)}\left[(V_G-V_T)V_D-\dfrac{V_D^2}{2}\right]$ (the printed formula uses diameters whose ratio equals $r_2/r_1$). (b) Show it reduces to (17.17) for $r_2=r_1+L$, $Z=2\pi r_1$, $L/r_1\ll1$. **Solution (a).** Use cylindrical coordinates, source inside at $r_1$, drain outside at $r_2$ (the result is the same if reversed). Current flows radially. Replace $y\to r$ and the width $Z\to2\pi r$ (circumference at radius $r$). $$J_{Nr}=-q\mu_nn\frac{d\phi}{dr}\qquad(\text{17.7 in }r)$$ $$I_D=-(2\pi r)\bar\mu_nQ_N(r)\frac{d\phi}{dr}\qquad(\text{17.9 with }Z\to2\pi r)$$ $I_D$ is independent of $r$; separate variables: $$I_D\frac{dr}{r}=-2\pi\bar\mu_nQ_N\,d\phi$$ $$I_D\int_{r_1}^{r_2}\frac{dr}{r}=-2\pi\bar\mu_n\int_0^{V_D}Q_N\,d\phi$$ $$I_D\ln\frac{r_2}{r_1}=2\pi\bar\mu_nC_o\int_0^{V_D}(V_G-V_T-\phi)\,d\phi\qquad(Q_N=-C_o(V_G-V_T-\phi))$$ $$\boxed{I_D=\frac{2\pi\bar\mu_nC_o}{\ln(r_2/r_1)}\left[(V_G-V_T)V_D-\frac{V_D^2}{2}\right]}$$ **(b)** With $r_2=r_1+L$: $\ln(r_2/r_1)=\ln(1+L/r_1)\approx L/r_1$ for $L/r_1\ll1$ (series $\ln(1+u)\approx u$). Then $$\frac{2\pi}{\ln(r_2/r_1)}\approx\frac{2\pi r_1}{L}=\frac{Z}{L}$$ which gives $I_D=\frac{Z\bar\mu_nC_o}{L}[(V_G-V_T)V_D-V_D^2/2]$, i.e. (17.17). ## Problem 17.12: Temperature dependence of the saturation current **Problem.** Ideal n-channel MOSFET, $x_o=0.1\ \mu$m, $N_A=10^{16}$ cm$^{-3}$ (OCR: "$10^1$"; taken as $10^{16}$, consistent with Problem 17.5). Assume the channel $\bar\mu_n$ has the same temperature dependence as the bulk $\mu_n$. (a) Find $I_{Dsat}(T)/I_{Dsat}(300\text{ K})$ with square-law theory. (b) For $V_G=3$ V compute and plot it for $200\le T\le400$ K with $\mu_n(T)/\mu_n(300)$ superimposed; repeat for $V_G=10$ V; discuss. **Solution (a).** $$I_{Dsat}(T)=\frac{Z\bar\mu_n(T)C_o}{2L}\,[V_G-V_T(T)]^2$$ $Z$, $L$, $C_o$ do not depend on $T$. Taking the ratio: $$\boxed{\frac{I_{Dsat}(T)}{I_{Dsat}(300)}=\frac{\mu_n(T)}{\mu_n(300)}\left[\frac{V_G-V_T(T)}{V_G-V_T(300)}\right]^2}$$ **(b)** Assumption: $\mu_n(T)\propto T^{-3/2}$ (lattice scattering), so $\mu_n(T)/\mu_n(300)=(T/300)^{-3/2}$. $V_T(T)$ is from the Problem 17.5 program ($V_T=2.43,\,2.29,\,2.13,\,1.96,\,1.79$ V at $T=200,250,300,350,400$ K). ```matlab close; clear q=1.6e-19; e0=8.85e-14; Ks=11.8; Ko=3.9; k=8.617e-5; Eg=1.12; xo=0.1e-4; NA=1e16; Co=Ko*e0/xo; T=200:5:400; ni=1e10*(T/300).^1.5.*exp(-(Eg/(2*k))*(1./T-1/300)); phiF=k*T.*log(NA./ni); VT=2*phiF+sqrt(4*q*Ks*e0*NA*phiF)/Co; VT300=VT(T==300); mu=(T/300).^(-1.5); for VG=[3 10] figure ratio=mu.*((VG-VT)/(VG-VT300)).^2; plot(T,ratio,T,mu,'--'); grid xlabel('T (K)'); ylabel('ratio'); title(['VG = ' num2str(VG) ' V']) legend('IDsat(T)/IDsat(300)','mu(T)/mu(300)') end ``` Computed values: | $T$ (K) | $\mu_n(T)/\mu_n(300)$ | $I_{Dsat}$ ratio, $V_G=3$ V | $I_{Dsat}$ ratio, $V_G=10$ V | |---|---|---|---| | 200 | 1.84 | 0.78 | 1.70 | | 300 | 1.00 | 1.00 | 1.00 | | 400 | 0.65 | 1.25 | 0.71 | **Discussion.** Two competing effects: the mobility falls with $T$, but $V_T$ also falls with $T$, which **raises** the overdrive $V_G-V_T$. At $V_G=3$ V the overdrive is small (0.87 V at 300 K), so a given change in $V_T$ is a large *fractional* change in overdrive: the $V_T$ effect wins and $I_{Dsat}$ **increases** with $T$. At $V_G=10$ V the overdrive (7.9 V) is large and barely changes, so the mobility effect wins, the current follows the mobility curve (slightly flattened) and **decreases** with $T$. At a particular intermediate gate voltage the two effects cancel and $I_{Dsat}$ is temperature independent (a "zero-temperature-coefficient" bias point, useful in circuit design). Large-signal power MOSFETs run at high overdrive, so they have a negative temperature coefficient, which prevents thermal runaway. ## Problem 17.13: Source and drain series resistances **Problem.** Resistances $R_S$ and $R_D$ (contact plus island resistance) lie between the terminals and the channel. Show the square-law theory accounts for them by replacing $V_D\to V_D-I_D(R_S+R_D)$ and $V_G\to V_G-I_DR_S$ in (17.17), (17.21), (17.22). **Solution.** The intrinsic channel potentials are (Fig. P17.13): at the intrinsic source ($y=0$) $\phi(0)=I_DR_S$; at the intrinsic drain ($y=L$) $\phi(L)=V_D-I_DR_D$. The gate-to-channel voltage is $V_G-\phi$ as before, so $Q_N=-C_o(V_G-V_T-\phi)$ still holds. Integrate (17.11) between the new limits: $$I_D=\frac{Z\bar\mu_nC_o}{L}\int_{I_DR_S}^{V_D-I_DR_D}(V_G-V_T-\phi)\,d\phi$$ $$=\frac{Z\bar\mu_nC_o}{L}\left[(V_G-V_T)(\phi_L-\phi_0)-\frac{\phi_L^2-\phi_0^2}{2}\right]\qquad\phi_0=I_DR_S,\ \phi_L=V_D-I_DR_D$$ Define $V_D'\equiv\phi_L-\phi_0=V_D-I_D(R_S+R_D)$. Then $\phi_L+\phi_0=V_D'+2I_DR_S$, so $$\frac{\phi_L^2-\phi_0^2}{2}=\frac{V_D'(V_D'+2I_DR_S)}{2}=V_D'\left(\frac{V_D'}{2}+I_DR_S\right)$$ $$I_D=\frac{Z\bar\mu_nC_o}{L}\,V_D'\left[(V_G-V_T)-I_DR_S-\frac{V_D'}{2}\right]$$ With $V_G'\equiv V_G-I_DR_S$: $$\boxed{I_D=\frac{Z\bar\mu_nC_o}{L}\left[(V_G'-V_T)V_D'-\frac{V_D'^2}{2}\right]}$$ which is (17.17) with $V_D\to V_D'$, $V_G\to V_G'$. Pinch-off: $Q_N(L)=0$ gives $\phi_L=V_G-V_T$, i.e. $V_D'+I_DR_S=V_G-V_T$, i.e. $$V_{Dsat}'=V_G'-V_T\quad(17.21),\qquad I_{Dsat}=\frac{Z\bar\mu_nC_o}{2L}(V_G'-V_T)^2\quad(17.22).$$ (Because $I_D$ appears on both sides, the equations are implicit; the resistances reduce the current and the effect grows as $L$ shrinks, since the channel resistance becomes comparable to $R_S+R_D$.) ## Problem 17.14: Derive Eq. (17.29) **Problem.** Derive $V_{Dsat}$ for the bulk-charge theory. **Solution.** Pinch-off: $Q_N(L)=0$ with $\phi(L)=V_{Dsat}$ in (17.27): $$V_G-V_T-V_{Dsat}-V_W\left[\sqrt{1+\frac{V_{Dsat}}{2\phi_F}}-1\right]=0$$ Let $s=\sqrt{1+V_{Dsat}/2\phi_F}$, so $V_{Dsat}=2\phi_F(s^2-1)$: $$V_G-V_T-2\phi_Fs^2+2\phi_F-V_Ws+V_W=0$$ $$2\phi_Fs^2+V_Ws-(V_G-V_T+V_W+2\phi_F)=0$$ Using $V_T=2\phi_F+V_W$ (ideal), $V_G-V_T+V_W+2\phi_F=V_G$: $$2\phi_Fs^2+V_Ws-V_G=0$$ $$s=\frac{-V_W+\sqrt{V_W^2+8\phi_FV_G}}{4\phi_F}\qquad(\text{positive root})$$ Then from the quadratic, $2\phi_Fs^2=V_G-V_Ws$, so $V_{Dsat}=V_G-V_Ws-2\phi_F$: $$\boxed{V_{Dsat}=V_G-2\phi_F+\frac{V_W^2}{4\phi_F}-\frac{V_W}{4\phi_F}\sqrt{V_W^2+8\phi_FV_G}}$$ Check: $V_G=3$, $\phi_F=0.358$, $V_W=0.71$ gives $1.14$ V (Exercise 17.3). Small-$V_W$ check: $\sqrt{V_W^2+8\phi_FV_G}\approx\sqrt{8\phi_FV_G}$, expanding for $V_W\to0$ gives $V_{Dsat}\to V_G-2\phi_F-\ldots\to V_G-V_T$, the square-law result. ## Problem 17.15: Bulk-charge $I_D$–$V_D$ program **Problem.** Write a program that plots $I_D/(Z\bar\mu_nC_o/L)$ versus $V_D$ from the bulk-charge theory and verify the Fig. 17.9 curves ($x_o=0.1\ \mu$m, $T=300$ K, $N_A=10^{14}$ and $10^{16}$ cm$^{-3}$). **Solution (logic).** For each $N_A$ and each overdrive $V_{GT}=V_G-V_T$ ($=1,2,3,4$ V): compute $\phi_F$, $C_o$, $V_W$, $V_T=2\phi_F+V_W$, $V_G=V_T+V_{GT}$; compute $V_{Dsat}$ from (17.29); evaluate (17.28) (normalized by $Z\bar\mu_nC_o/L$) on $0\le V_D\le V_{Dsat}$; append a flat tail at $I_{Dsat}$ out to $V_D=12$ V. Compare against the square law curves of Exercise 17.2. ```matlab close; clear q=1.6e-19; e0=8.85e-14; Ks=11.8; Ko=3.9; kT=0.0259; ni=1e10; xo=0.1e-4; Co=Ko*e0/xo; NAs=[1e14 1e16]; sty={'--',':'}; for ia=1:2 NA=NAs(ia); phiF=kT*log(NA/ni); Vw=sqrt(4*q*Ks*e0*NA*phiF)/Co; VT=2*phiF+Vw; for VGT=1:4 VG=VT+VGT; VDsat=VG-2*phiF+Vw^2/(4*phiF)-(Vw/(4*phiF))*sqrt(Vw^2+8*phiF*VG); VD=linspace(0,VDsat); ID=(VGT+Vw)*VD-VD.^2/2-(4*phiF*Vw/3)*((1+VD/(2*phiF)).^1.5-1); VD=[VD 12]; ID=[ID ID(end)]; plot(VD,ID,sty{ia}); hold on end end for VGT=1:4 % square law for comparison VD=[linspace(0,VGT) 12]; ID=[VGT*VD(1:end-1)-VD(1:end-1).^2/2, VGT^2/2]; plot(VD,ID,'-') end grid; xlabel('VD (volts)'); ylabel('ID/(Z mu Co/L)'); hold off ``` Expected result: the bulk-charge curves lie below the square-law curves (reduced $I_D$ and $V_{Dsat}$); the $N_A=10^{14}$ curves nearly coincide with the square law (small $V_W$), while the $10^{16}$ curves (for $x_o=0.1\ \mu$m: $V_Wpprox1.42$ V, versus $V_Wpprox0.12$ V at $10^{14}$) are noticeably lower, e.g. at $V_{GT}=4$ the saturation level is clearly under 8, as in Fig. 17.9. ## Problem 17.16: Charge-sheet and exact-charge $I_D$–$V_D$ **Problem.** Using the Appendix D relationships, write programs for $I_D$–$V_D$ from (a) charge-sheet theory, (b) exact-charge theory, and compare with Figs. 17.10 and 17.11. **Note on the data.** Appendix D is not in the supplied text. The programs below implement the standard equivalent formulation, which gives the same physics: gradual-channel approximation with the electron quasi-Fermi potential $V_c(y)$ (0 at the source, $V_D$ at the drain) as the independent variable. Drift plus diffusion combine into $$I_D=\frac{Z\bar\mu_n}{L}\int_0^{V_D}\left[-Q_N(V_G,V_c)\right]dV_c$$ The integrand must be found at each $V_c$. **Step 1: surface potential.** With $V_t=kT/q$, $A=\sqrt{2qK_S\epsilon_0N_A}$ and (ideal, $V_{FB}=0$), $\psi_s$ satisfies charge balance $C_o(V_G-\psi_s)=A\,F(\psi_s,V_c)$ where - *Exact-charge* (full Poisson solution): $$F^2=\psi_s+V_t\left(e^{-\psi_s/V_t}-1\right)+e^{-2\phi_F/V_t}\,V_t\,e^{-V_c/V_t}\left(e^{\psi_s/V_t}-1\right)$$ - *Charge-sheet* (neglect the hole terms below the sheet; electrons treated as a sheet at the surface): $$F^2\approx\psi_s+V_t\,e^{(\psi_s-2\phi_F-V_c)/V_t}$$ **Step 2: channel charge.** - Charge-sheet: $Q_N=-A\left[F(\psi_s)-\sqrt{\psi_s}\right]$ (total charge minus the depletion-approximation bulk charge $-A\sqrt{\psi_s}$). - Exact: integrate the electron density through the semiconductor, using Gauss's law $\mathcal E(\psi)=\sqrt{2qN_A/K_S\epsilon_0}\,F(\psi)$ and $n(\psi)=n_{p0}e^{(\psi-V_c)/V_t}$, $n_{p0}=n_i^2/N_A$: $$Q_N=-q\int_0^{\psi_s}\frac{n(\psi)}{\mathcal E(\psi)}\,d\psi$$ (with $\psi=u^2$ to remove the $1/\sqrt\psi$ end-point singularity). **Step 3:** integrate over $V_c$ with `trapz`. Both models self-saturate (no artificial post-pinch-off construction) because at $V_c\approx V_G-V_T$ the sheet charge simply vanishes and the integrand becomes small. They also give a nonzero subthreshold current for $V_G<V_T$. ```matlab % Charge-sheet and exact-charge ID-VD (n-channel, cgs units) close; clear q=1.6e-19; e0=8.85e-14; Ks=11.8; Ko=3.9; Vt=0.0259; ni=1e10; NA=1e15; xo=0.05e-4; mu=550; Z=70e-4; L=7e-4; % Fig. 17.10 device Co=Ko*e0/xo; phiF=Vt*log(NA/ni); A=sqrt(2*q*Ks*e0*NA); npo=ni^2/NA; Fcs = @(p,Vc) sqrt(p + Vt*exp((p-2*phiF-Vc)/Vt)); Fex = @(p,Vc) sqrt(max(p + Vt*expm1(-p/Vt) + ... exp(-2*phiF/Vt)*Vt*exp(-Vc/Vt).*expm1(p/Vt), 1e-30)); VD = 0:0.25:9; figure; hold on for VG = 2:5 for model = 1:2 % 1 = charge sheet, 2 = exact ID = zeros(size(VD)); for k = 1:numel(VD) Vc = linspace(0,VD(k),40); integrand = zeros(size(Vc)); for j = 1:numel(Vc) F = Fcs; if model==2, F = Fex; end g = @(p) Co*(VG-p) - A*F(p,Vc(j)); ps = fzero(g,[1e-9 max(VG,1e-3)]); % surface potential if model==1 QN = -A*(F(ps,Vc(j)) - sqrt(ps)); else f = @(u) npo*exp((u.^2-Vc(j))/Vt)./ ... (sqrt(2*q*NA/(Ks*e0))*F(u.^2,Vc(j))).*2.*u; QN = -q*integral(f,0,sqrt(ps)); end integrand(j) = -QN; end if VD(k)>0, ID(k) = Z*mu/L*trapz(Vc,integrand); end end if model==1, plot(VD,ID*1e3,'--'); else, plot(VD,ID*1e3,'-'); end end end xlabel('V_D (volts)'); ylabel('I_D (mA)'); grid; hold off ``` Subthreshold check (Fig. 17.11): loop `VG = -0.6:0.05:0.5`, set `VD = 1`, and plot `semilogy(VG,ID)`. With the same code, $I_D$ falls exponentially at roughly $60\text{--}80$ mV per decade below $V_T$ rather than dropping abruptly to zero. Expected results (computed for the Fig. 17.10 device, $V_D=5$ V): $I_D\approx0.18$ mA ($V_G=2$ V), $0.60$–$0.68$ mA (3 V), $1.5$–$2.7$ mA (5 V depending on model details), in saturation by $V_D\approx V_G-V_T$ and with the two theories nearly overlapping, as in Fig. 17.10. Treat the numbers as approximate since exact agreement with the book's Appendix D equations cannot be guaranteed. ## Problem 17.17: Verify the bulk-charge entries of Table 17.1 **Solution.** Start from (17.28), $\xi=Z\bar\mu_nC_o/L$: $$I_D=\xi\left\{(V_G-V_T+V_W)V_D-\frac{V_D^2}{2}-\frac{4\phi_FV_W}{3}\left[\left(1+\frac{V_D}{2\phi_F}\right)^{3/2}-1\right]\right\}$$ **$g_d$ below pinch-off.** $$g_d=\left.\frac{\partial I_D}{\partial V_D}\right|_{V_G}=\xi\left\{V_G-V_T+V_W-V_D-\frac{4\phi_FV_W}{3}\cdot\frac32\cdot\frac{1}{2\phi_F}\left(1+\frac{V_D}{2\phi_F}\right)^{1/2}\right\}$$ $$\boxed{g_d=\xi\left[V_G-V_T-V_D+V_W\left(1-\sqrt{1+\frac{V_D}{2\phi_F}}\right)\right]}$$ (the factor: $\frac{4\phi_F}{3}\cdot\frac32\cdot\frac1{2\phi_F}=1$). **$g_m$ below pinch-off.** $V_G$ appears only in $(V_G-V_T+V_W)V_D$, so $$g_m=\left.\frac{\partial I_D}{\partial V_G}\right|_{V_D}=\xi V_D$$ **Above pinch-off.** $I_D=I_{Dsat}(V_G)=I_D(V_D=V_{Dsat}(V_G),V_G)$ is independent of $V_D$, so $g_d=0$. By the chain rule: $$g_m=\frac{dI_{Dsat}}{dV_G}=\left.\frac{\partial I_D}{\partial V_G}\right|_{V_D=V_{Dsat}}+\underbrace{\left.\frac{\partial I_D}{\partial V_D}\right|_{V_D=V_{Dsat}}}_{=\,g_d(V_{Dsat})=0}\frac{dV_{Dsat}}{dV_G}=\xi V_{Dsat}$$ The second term vanishes because $g_d(V_{Dsat})=-Z\bar\mu_nQ_N(L)/L=0$ at pinch-off. $\blacksquare$ (Square-law entries follow the same way with $V_W=0$: $g_d=\xi(V_G-V_T-V_D)$, $g_m=\xi V_D$ below pinch-off, and $g_m=\xi(V_G-V_T)$ above.) ## Problem 17.18: Inversion charge and drain conductance **Problem.** $V_G=3$ V, $V_D=0$, $Z=70\ \mu$m, $L=7\ \mu$m, $\bar\mu_n=550$ cm$^2$/V-s, $x_o=0.05\ \mu$m, $V_T=1$ V. Square-law: (a) inversion charge per cm$^2$ at $y=L/2$; (b) $g_d$. **Solution.** $C_o=\dfrac{(3.9)(8.85\times10^{-14})}{5\times10^{-6}}=6.90\times10^{-8}$ F/cm$^2$. **(a)** With $V_D=0$ the channel potential is zero everywhere, $\phi(L/2)=0$: $$Q_N(L/2)=-C_o(V_G-V_T-\phi)=-(6.90\times10^{-8})(3-1-0)=-1.38\times10^{-7}\ \text{C/cm}^2$$ (about $8.6\times10^{11}$ electrons/cm$^2$). **(b)** $$g_d=\frac{Z\bar\mu_nC_o}{L}(V_G-V_T-V_D)=\frac{70}{7}(550)(6.90\times10^{-8})(2)=7.59\times10^{-4}\ \text{S}\approx0.76\ \text{mS}$$ ## Problem 17.19: Complementary pair **Problem.** n-channel: $Z=50\ \mu$m, $L=5\ \mu$m, $x_o=0.05\ \mu$m, $N_A=10^{16}$ cm$^{-3}$. The p-channel device has the same oxide thickness and doping (donors $N_D=10^{16}$) and must have the same $g_m$ at equivalent bias and $T=300$ K. Find $Z$ and $L$ of the p-channel device. Effective mobility is half the bulk mobility in both. **Solution.** Assumed bulk mobilities (lightly doped Si, 300 K): $\mu_n=1350$, $\mu_p=480$ cm$^2$/V-s (so effective values 675 and 240). Equal $x_o$ gives equal $C_o$; "equivalent bias" means equal overdrive magnitudes (same $|V_G-V_T|$ and $|V_D|$; the ideal $|V_T|$ is equal for equal doping). Since $g_m\propto(Z/L)\bar\mu\,C_o|V_D|$ (or $|V_G-V_T|$): $$\left(\frac{Z}{L}\right)_p\bar\mu_p=\left(\frac{Z}{L}\right)_n\bar\mu_n$$ $$\left(\frac{Z}{L}\right)_p=\left(\frac{Z}{L}\right)_n\frac{\mu_n^{bulk}/2}{\mu_p^{bulk}/2}=10\cdot\frac{1350}{480}=28.1$$ Choose the same (minimum) length $L_p=5\ \mu$m; then $Z_p=28.1\times5=140.6\ \mu$m, about **2.8 times wider** than the n-channel device. (Alternatively keep $Z_p=50\ \mu$m and shorten $L_p=1.78\ \mu$m, but then $f_{max}$ and other L-dependent properties no longer match, and $L$ is normally set to the technology minimum.) With 1350/480 the width ratio is $2.8$; if the bulk-mobility ratio used is $1500/600$ it becomes $2.5$. ## Problem 17.20: General MOSFET review **Problem.** Fig. P17.20 shows $I_D$–$V_D$ with $I_{Dsat}=10^{-3}$ A, $V_{Dsat}=5$ V, and three marked points. (The points' positions are not recoverable from the OCR. Assumption used here: point (1) lies in the rising region below pinch-off, point (2) also in the rising region at $V_D=2.5$ V, and point (3) lies in saturation at $V_D=10$ V, the right end of the axis. Formulas are given in general form so other positions can be substituted.) **Solution.** Square law: $V_{Dsat}=V_G-V_T=5$ V and $I_{Dsat}=\frac{\xi}{2}(5)^2=10^{-3}$ A: $$\xi=\frac{2I_{Dsat}}{(V_G-V_T)^2}=\frac{2\times10^{-3}}{25}=8\times10^{-5}\ \text{A/V}^2$$ **(a)** At point (1) (below pinch-off, $0<V_D<5$ V): inversion layer is a strip under the oxide connecting $n^+$ source and $n^+$ drain, **thick at the source and gradually thinner toward the drain but still nonzero at the drain end**. The depletion region (p-substrate) below it has constant minimum width at the source and widens toward the drain. Label the gate, oxide, $n^+$ source/drain, p-Si, inversion layer, depletion region, $L$, and the (absent) pinch-off point. **(b)** $V_G=V_T+V_{Dsat}=1+5=6$ V. **(c)** $x_o=0.1\ \mu$m: $C_o=\dfrac{(3.9)(8.85\times10^{-14})}{10^{-5}}=3.45\times10^{-8}$ F/cm$^2$. The charge at the drain end is $Q_N(L)=-C_o(V_G-V_T-V_D)$. At the assumed point (2), $V_D=2.5$ V: $$Q_N(L)=-(3.45\times10^{-8})(5-2.5)=-8.6\times10^{-8}\ \text{C/cm}^2$$ (If (2) were at $V_D\ge5$ V, i.e. at or beyond pinch-off, $Q_N(L)=0$.) **(d)** New overdrive $V_G-V_T=3$ V gives $V_{Dsat}=3$ V. $V_D=4$ V exceeds it, so the device is saturated: $$I_D=\frac{\xi}{2}(3)^2=\frac{8\times10^{-5}}{2}(9)=3.6\times10^{-4}\ \text{A}$$ **(e)** At the assumed saturated point (3), $g_d=0$. (If (3) were below pinch-off at $V_D$: $g_d=\xi(5-V_D)$.) **(f)** Saturated: $g_m=\xi V_{Dsat}=(8\times10^{-5})(5)=0.4$ mS (equivalently $2I_{Dsat}/(V_G-V_T)=0.4$ mS). (If below pinch-off: $g_m=\xi V_D$.) **(g)** $C_G$ versus $V_G$ with $V_D=0$: a **low-frequency MOS-C curve**. For $V_G\ll V_T$ (accumulation; for the ideal device, $V_G<0$) $C_G=C_oZL$ (maximum). In depletion it drops toward a minimum $C_{min}=\dfrac{C_oC_{dep}}{C_o+C_{dep}}ZL$ near $V_G\approx V_T$ (the minimum occurs slightly below $V_T$). In inversion ($V_G>V_T$) it rises back to $C_oZL$, because the source/drain islands supply electrons and the inversion layer screens the gate. So the shape is a flat high plateau, a dip around $0\le V_G\le V_T$, and a return to the same plateau. ## Problem 17.21: Small-signal characteristics **Problem.** Using the square-law entries of Table 17.1 and neglecting $\bar\mu_n(V_G)$, draw (one coordinate system per part): (a) $g_d/\xi$ versus $V_G$ ($0\le V_G\le5$ V) for $V_T=1$ V and $V_D=0,1,2$ V; (b) $g_d/\xi$ versus $V_D$ ($0\le V_D\le5$ V) for $V_G-V_T=1,2,3$ V; (c) $g_m/\xi$ versus $V_D$ ($0\le V_D\le5$ V) for $V_G-V_T=1,2,3$ V. **Solution.** **(a)** $g_d/\xi=V_G-V_T-V_D$ when $V_G-V_T\ge V_D$ (below pinch-off), and $0$ when $V_G-V_T<V_D$ (saturation or off). - $V_D=0$: zero for $V_G<1$ V, then a straight line of slope 1: $g_d/\xi=V_G-1$ (reaching 4 at $V_G=5$). - $V_D=1$ V: zero until $V_G=2$ V, then $V_G-2$ (reaching 3 at 5 V). - $V_D=2$ V: zero until $V_G=3$ V, then $V_G-3$ (reaching 2 at 5 V). Three parallel lines of slope 1, shifted right by $V_D$. Extrapolation of the $V_D=0$ line to the axis gives $V_T$ (as in Fig. 17.13a). **(b)** $g_d/\xi=(V_G-V_T)-V_D$ for $V_D\le V_G-V_T$, else 0. Each curve starts at $V_G-V_T$ at $V_D=0$ (1, 2, 3), decreases linearly with slope $-1$ and hits zero at $V_D=V_{Dsat}=V_G-V_T$ (at 1, 2, 3 V), then stays zero. **(c)** $g_m/\xi=V_D$ for $V_D\le V_G-V_T$ and $=V_G-V_T$ for $V_D>V_G-V_T$. Each curve is a straight line of slope 1 up to $V_D=V_G-V_T$ (1, 2, 3 V), then flat at the value $V_G-V_T$ (1, 2, 3). ```matlab VT=1; xi=1; VD=linspace(0,5,501); VG=linspace(0,5,501); % (a) figure; hold on for vd=[0 1 2] gd=xi*max(VG-VT-vd,0).*(VG-VT>=vd); plot(VG,gd); end xlabel('V_G (V)'); ylabel('g_d/(Z mu Co/L)'); grid; hold off % (b),(c) figure; hold on for vgt=[1 2 3] gd=xi*max(vgt-VD,0); plot(VD,gd); end xlabel('V_D (V)'); ylabel('g_d/(Z mu Co/L)'); grid; hold off figure; hold on for vgt=[1 2 3] gm=xi*min(VD,vgt); plot(VD,gm); end xlabel('V_D (V)'); ylabel('g_m/(Z mu Co/L)'); grid; hold off ``` ## Problem 17.22: Compare the MOSFET and the J-FET **Solution.** **Similarities.** - Both are majority-carrier, **voltage-controlled** unipolar devices with source, drain and gate terminals. A gate voltage modulates the conductance of a channel between source and drain. - Both have a **linear** region (channel behaves like a resistor, $I_D\propto V_D$ at small $V_D$) followed by sloping-over due to channel narrowing and **saturation after pinch-off**, where the pinched-off section absorbs the excess drain voltage. - Both have the gate input essentially open at low frequency (no d.c. gate current; reverse-biased junction in the J-FET, insulator in the MOSFET). Same small-signal circuit ($g_d$, $g_m$, $C_{gs}$, $C_{gd}$) and the same $f_{max}\sim g_m/2\pi C_G\propto1/L^2$. - Analysis follows the same gradual-channel method: integrate the local current equation along the channel from source to drain with a position-dependent channel charge, giving a square-law relation near saturation. $g_d$ and $g_m$ are defined identically. **Differences.** - *Structure and gate:* J-FET: the gate is a pn junction (or Schottky) and the channel is a **physical bulk n- or p-region** between depletion regions. MOSFET: the gate is an insulated MOS capacitor, and the channel is a **gate-induced surface inversion layer** that did not exist before the gate voltage was applied. - *How the gate controls the channel:* J-FET: the gate bias changes the **depletion width**, narrowing a built-in channel (normally-on, depletion mode). MOSFET: the gate bias changes the **inversion charge**; the standard device is **enhancement mode** (normally off, $V_T>0$ for n-channel). - *Gate polarity:* J-FET gates must be kept reverse biased (otherwise large gate current). MOSFET gate may be of either polarity, subject to oxide breakdown. - *Input impedance:* MOSFET is far higher (oxide leakage is tiny); J-FET limited by junction leakage. - *Transport:* J-FET carriers move in the bulk (bulk mobility); MOSFET carriers move in a surface layer and have an **effective mobility** reduced by surface scattering, which depends on $V_G$. - *Analysis:* J-FET: the channel charge is set by the depletion width $W(y)$ (the relation between $V_G$, $V_D$ and the channel opening $h(y)$, with pinch-off when the channels close), giving $I_D\propto(V_P-V_G)^2$-type results with the pinch-off voltage $V_P$. MOSFET: charge balance via $C_o$ (square law), with a second-order bulk-charge correction, a threshold voltage $V_T$, and the subthreshold current. - *Integration and application:* The MOSFET is easy to miniaturize and to build into dense complementary integrated circuits, so it dominates digital ICs and memories. J-FETs are used mostly as discrete low-noise amplifiers and analog switches.