part13

Chapter 16: MOS Fundamentals

Constants used throughout (as the book instructs): $T=300\text{K}$, $kT/q=0.0259\text{V}$, $n_i=10^{10}{\text{cm}}^{-3}$, $K_S=11.8$, $K_O=3.9$, ${\epsilon }_0=8.85\times 10^{-14}\text{F/cm}$, $q=1.6\times 10^{-19}\text{C}$.

Imagine a sandwich: a metal slice, a whisper-thin sheet of glass, and a slab of silicon. That sandwich, the metal-oxide-semiconductor (MOS) structure, sits at the heart of nearly every chip made today. A processor with billions of transistors is, at bottom, billions of these sandwiches. The idea of a “field effect” device dates to the 1920s, but modern history begins with Kahng and Atalla, who filed patents on the Si-SiO${}_2$ field-effect transistor in 1960. “MOS” is reserved for the metal-SiO${}_2$-Si system; the generic name MIS (metal-insulator-semiconductor) covers other insulators or semiconductors.

This chapter studies the simplest MOS device, the two-terminal MOS capacitor (MOS-C). The plan:

1. Define precisely an ideal MOS-C.
2. Draw energy-band and block-charge pictures of what happens inside under a static bias.
3. Turn the pictures into equations (charge, field, potential), and link them to the gate voltage.
4. Explain the capacitance-voltage ($C$-$V$) curve, the “window” through which engineers look inside the sandwich.

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16.1 Ideal Structure Definition

The MOS-C (Fig. 16.1) is a thin SiO${}_2$ layer (0.01 $\mu$m to 1.0 $\mu$m) between a Si substrate and a metallic field plate. Common field-plate materials are aluminum and heavily doped polycrystalline silicon (polysilicon, deposited by chemical vapor deposition and then heavily n- or p-doped by diffusion or ion implantation). A second metallic layer on the back gives electrical contact to the silicon. The field plate and its terminal are the gate; the silicon terminal, normally grounded, is the back or substrate contact. $x$ is measured from the oxide-semiconductor interface into the silicon; $x_o$ is the oxide thickness; $V_G$ is the gate voltage.

Eight idealizations define the ideal MOS-C:

1. The gate is thick enough to be an equipotential region, under a.c. as well as d.c. bias.
2. The oxide is a perfect insulator: zero current through it under all static biases.
3. There are no charge centers in the oxide or at the oxide-semiconductor interface.
4. The semiconductor is uniformly doped.
5. The semiconductor is thick enough that, whatever the gate potential, a field-free region (the “bulk”) is reached before the back contact.
6. The back contact is ohmic.
7. The structure is one-dimensional; everything depends only on $x$.
8. ${\Phi }_M={\Phi }_S=\chi +(E_C-E_F{)}_{FB}$: the metal and semiconductor work functions are equal.

Are these realistic? Largely yes: SiO${}_2$ resistivity can reach $10^{18}\Omega \cdot$cm, so d.c. leakage is negligible; thin gates are equipotential; ohmic backs are easy. Idealization 8 is the exception. It is only a convenience, and Chapter 18 removes it. Its purpose here is to avoid early clutter in the static description.

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16.2 Electrostatics: Mostly Qualitative

16.2.1 Visualization Aids

Energy band diagram

Think of each component as a “city skyline” of energies ending at a vertical wall (the surface). The ledge at the top of the wall is the vacuum level $E_0$, the minimum energy an electron needs to escape the material completely (Fig. 16.2).

• Metal: the gap between $E_0$ and $E_F$ is the work function ${\Phi }_M$.
• Semiconductor: the barrier is given by the electron affinity $\chi =E_0-E_C$ at the surface. Why $\chi$ and not $E_0-E_F$? Because $E_0-E_F$ changes with doping and band bending, whereas $\chi$ does not. The flat-band (field-free) interior has $(E_C-E_F{)}_{FB}$, so the semiconductor work function is ${\Phi }_S=\chi +(E_C-E_F{)}_{FB}$.
• Insulator: modeled as an intrinsic wide-gap semiconductor with its own electron-affinity barrier.

Building the zero-bias diagram in two steps.

1. Bring the metal and semiconductor together to a gap of $x_o$ and let them equilibrate. The Fermi levels must align (Subsection 3.2.4). Because ${\Phi }_M={\Phi }_S$, the vacuum levels also align, so there is no net charge and no field anywhere in the gap.
2. Insert the insulator into the empty gap. With zero field in the gap, inserting it only lowers the barrier between M and S slightly.

The result (Fig. 16.3) is a flat diagram: $E_F$ flat, $E_C$ and $E_V$ flat in the semiconductor, with a rectangular barrier through the oxide.

Block charge diagrams

These show roughly where charge sits. They are squared-off (block) approximations, so magnitudes and extents are qualitative. One rule is exact: the fields vanish in the interior of metal and semiconductor (idealization 5), so by Gauss’s law total charge is zero. Hence the area of the positive blocks always equals the area of the negative blocks. Under equilibrium (zero bias) the ideal structure has no charge at all.

16.2.2 Effect of an Applied Bias

General observations

Ground the back and apply $V_G$ to the gate. Three rules follow.

1. The semiconductor Fermi level stays flat. Zero current flows under static bias, so the semiconductor is always in equilibrium regardless of $V_G$.
2. The Fermi levels at the two ends separate by $q{V}_G$: E_F(\text{metal})-E_F(\text{semiconductor})=-qV_G \tag{16.1} Picture the two Fermi levels as handles to the outside world. The back handle is fixed (grounded). You pull the metal handle down if $V_G>0$ and push it up if $V_G<0$.
3. Bands bend. The barrier heights are fixed, so moving the metal handle distorts the rest, like bending a rubber doll. The metal is an equipotential, so it has no bending. In the oxide and semiconductor the bands slope upward (energy increasing from gate toward back) when $V_G>0$ and downward when $V_G<0$. In the ideal oxide, Poisson’s equation gives $d{\mathcal{E}}_{ox}/dx=0$, so ${\mathcal{E}}_{ox}$ is constant: $E_C$ and $E_V$ in the oxide are straight lines. In the semiconductor the bending is more complex but must die out before the back contact.

Specific biasing regions (n-type substrate)

• Accumulation ($V_G>0$). $E_F$ in the metal drops. Bands slope upward toward the back, so they lie lower near the interface. Then $n=n_i{e}^{(E_F-E_i)/kT}$ increases toward the oxide: majority carriers pile up at the interface. Charge view: positive charge on the gate attracts electrons (Fig. 16.5a,b).
• Depletion (small $V_G<0$). A small negative bias lifts the metal $E_F$; bands slope downward. The electron concentration at the interface drops below $N_D$, and the hole concentration is still below $N_D$ too, so the surface is depleted: electrons are repelled, exposing positive donor ions (Fig. 16.5c,d).
• Onset of inversion. More negative $V_G$ bends the bands up at the surface more and more. The surface hole concentration $p_s$ rises: below $n_i$ while $E_i(\text{surface})<E_F$, equal to $n_i$ when $E_i(\text{surface})=E_F$, above $n_i$ once $E_i$ crosses above $E_F$. Eventually E_i(\text{surface})-E_i(\text{bulk})=2\left[E_F-E_i(\text{bulk})\right] \tag{16.2} which makes p_s=n_i e^{[E_i(\text{surface})-E_F]/kT}=n_i e^{[E_F-E_i(\text{bulk})]/kT}=n_{bulk}=N_D \tag{16.3} The surface hole concentration equals the bulk electron concentration. This happens at the special bias $V_G=V_T$ (the threshold voltage).
• Inversion ($V_G<V_T$). Now $p_s>n_{bulk}=N_D$: the minority carrier concentration at the surface exceeds the bulk majority concentration, and the surface region has changed character from n-type to p-type (Fig. 16.5g,h).

Summary for an ideal n-type device: accumulation for $V_G>0$, depletion for $V_T<V_G<0$, inversion for $V_G<V_T$. For an ideal p-type device all polarities are reversed (Fig. 16.6): accumulation for $V_G<0$, depletion for $0<V_G<V_T$, inversion for $V_G>V_T$ (with $V_T>0$). Flat band (no band bending, no semiconductor charge) at $V_G=0$ separates accumulation from depletion. The depletion-inversion transition is $V_G=V_T$, and Eq. (16.2) quantitatively specifies it for both types.

Why “inversion”? Think of a crowd at a theater. Accumulation: everyone crowds toward the stage. Depletion: people are pushed back, leaving the front rows empty. Inversion: the pushing is so strong that a different kind of audience (holes) fills the front rows. The front rows have inverted their identity.

Exercise 16.1

Problem. Construct line plots (with $V_G$ along the axis) identifying the voltage ranges for accumulation, depletion, and inversion in ideal n- and p-type MOS devices.

Solution. From the summary above, on the $V_G$ axis:

$\text{n-type: }\underset{\text{INV}}{\underbrace{V_G<V_T}}\left|\underset{\text{DEPL}}{\underbrace{V_T<V_G<0}}\right|\underset{\text{ACC}}{\underbrace{V_G>0}}$ $\text{p-type: }\underset{\text{ACC}}{\underbrace{V_G<0}}\left|\underset{\text{DEPL}}{\underbrace{0<V_G<V_T}}\right|\underset{\text{INV}}{\underbrace{V_G>V_T}}$

with $V_T<0$ for n-type and $V_T>0$ for p-type.

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16.3 Electrostatics: Quantitative Formulation

16.3.1 Semiconductor Electrostatics

Preparatory considerations

The goal is $\rho (x)$, $\mathcal{E}(x)$ and $\varphi (x)$ inside an ideal MOS-C. The metal charge sits within a few angstroms of the M-O interface (modeled as a $\delta$-function), and with no oxide charge its magnitude equals the sum of the semiconductor charges. In the oxide, $\mathcal{E}$ is constant and $\varphi$ is linear. So the work reduces to solving for the semiconductor.

We use the depletion approximation for a closed-form solution (an exact solution exists, Appendix B, because the semiconductor is always in equilibrium).

Definitions. $\varphi (x)$ is the potential at depth $x$ (the symbol $\varphi$ rather than $V$ avoids confusion with applied voltages). $\mathcal{E}=-d\varphi /dx\to 0$ deep in the bulk, and $\varphi$ is set to zero in the bulk. The value at the interface is the surface potential ${\varphi }_s=\varphi (0)$. Relations with band bending (Fig. 16.7):

\phi(x)=\frac{1}{q}\left[E_i(\text{bulk})-E_i(x)\right] \tag{16.4} \phi_s=\frac{1}{q}\left[E_i(\text{bulk})-E_i(\text{surface})\right] \tag{16.5} \phi_F\equiv\frac{1}{q}\left[E_i(\text{bulk})-E_F\right] \tag{16.6}

${\varphi }_F>0$ for p-type and ${\varphi }_F<0$ for n-type. For nondegenerate Si near room temperature: p_{bulk}=n_i e^{[E_i(\text{bulk})-E_F]/kT}=N_A\quad(N_A\gg N_D),\qquad n_{bulk}=n_i e^{[E_F-E_i(\text{bulk})]/kT}=N_D\quad(N_D\gg N_A) \tag{16.7} Combining (16.6) and (16.7): \phi_F=\frac{kT}{q}\ln\frac{N_A}{n_i}\ \ (\text{p-type}),\qquad \phi_F=-\frac{kT}{q}\ln\frac{N_D}{n_i}\ \ (\text{n-type}) \tag{16.8}

Flat band: ${\varphi }_s=0$. Substituting (16.5) and (16.6) into (16.2): \phi_s=2\phi_F\quad\text{at the depletion-inversion transition} \tag{16.9}

For a p-type semiconductor (${\varphi }_F>0$): ${\varphi }_s<0$ accumulation; $0<{\varphi }_s<2{\varphi }_F$ depletion; ${\varphi }_s>2{\varphi }_F$ inversion. For n-type the inequalities are reversed: ${\varphi }_s>0$ accumulation; $2{\varphi }_F<{\varphi }_s<0$ depletion; ${\varphi }_s<2{\varphi }_F$ inversion.

Exercise 16.2

Problem. (a) Plot ${\varphi }_s$ ranges for accumulation, depletion, inversion in n- and p-type devices. (b) For each set $({\varphi }_F/(kT/q),{\varphi }_s/(kT/q))$: (i) $(12,12)$, (ii) $(-9,3)$, (iii) $(-9,-18)$, (iv) $(15,36)$, (v) $(-15,0)$ (the OCR is garbled; pairs are inferred from the book’s answer table, which lists p, n, n, p, n with depletion, accumulation, depl/inv transition, inversion, flat band), state doping type and bias condition and draw the band and charge diagram.

Solution.

(a) $\text{n-type }({\varphi }_F<0):{\varphi }_s<2{\varphi }_F\text{INV};2{\varphi }_F<{\varphi }_s<0\text{DEPL};{\varphi }_s>0\text{ACC}$ $\text{p-type }({\varphi }_F>0):{\varphi }_s<0\text{ACC};0<{\varphi }_s<2{\varphi }_F\text{DEPL};{\varphi }_s>2{\varphi }_F\text{INV}$

(b) The sign of ${\varphi }_F$ gives the type.

Set	Doping	Test	Condition	Band diagram	Block charge
(i) 12, 12	p	$0<12<24$	Depletion	surface bands bent down by $12kT/q$	$+Q$ gate, $-Q$ ionized acceptors over width $W$
(ii) -9, 3	n	${\varphi }_s>0$	Accumulation	$E_C$ dips toward $E_F$ at the surface	$+Q$ gate, $-Q$ electron layer at interface
(iii) -9, -18	n	${\varphi }_s=2{\varphi }_F$	Depl/Inv transition	$E_i(s)-E_F=	\phi_F
(iv) 15, 36	p	$36>30$	Inversion	bands bent down strongly, $E_i(s)$ well below $E_F$	$+Q$ gate; $-Q$ electron layer plus acceptors over $W_T$
(v) -15, 0	n	${\varphi }_s=0$	Flat band	all flat	no charge

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Delta-depletion solution

Exact $\rho$ and $\varphi$ plots (Fig. 16.8, ${\varphi }_F=12kT/q$, $T=300$ K) show:

• Accumulation (a): the charge is squeezed into an extremely thin layer next to the interface.
• Middle of depletion (b), onset of inversion (c), deep inversion (d): the depleted region reaches far into the semiconductor; in inversion the minority charge is again in a thin layer. From depletion to onset the depletion width grows substantially, but beyond onset only slightly.

The delta-depletion model therefore:

• Accumulation: replace the layer by a $\delta$-function of equal charge at $x=0$. Then $\mathcal{E}=0$ and $\varphi =0$ for all $x>0$ (a first-order approximation).
• Inversion: replace the layer by a $\delta$-function at $x=0$ that exactly balances all gate charge added after onset. So $W$, $\mathcal{E}(x>0)$ and $\varphi (x>0)$ stay frozen at their ${\varphi }_s=2{\varphi }_F$ values.
• Depletion: squared-off charge ending abruptly at $x=W$.

Derivation for a p-type device in depletion.

\rho=q(p-n+N_D^+-N_A^-)=-qN_A\quad(0\le x\le W) \tag{16.10} Poisson’s equation, $d\mathcal{E}/dx=\rho /K_S{\epsilon }_0$: \frac{d\mathcal{E}}{dx}=-\frac{qN_A}{K_S\varepsilon_0}\quad(0\le x\le W) \tag{16.11} Integrate with $\mathcal{E}(W)=0$: \mathcal{E}(x)=\frac{qN_A}{K_S\varepsilon_0}(W-x)\quad(0\le x\le W) \tag{16.12} Since $\mathcal{E}=-d\varphi /dx$, integrate again with $\varphi (W)=0$: \phi(x)=\frac{qN_A}{2K_S\varepsilon_0}(W-x)^2\quad(0\le x\le W) \tag{16.13} Boundary condition $\varphi (0)={\varphi }_s$: \phi_s=\frac{qN_AW^2}{2K_S\varepsilon_0} \tag{16.14} W=\left[\frac{2K_S\varepsilon_0\phi_s}{qN_A}\right]^{1/2} \tag{16.15} For an n-type device replace $N_A\to -N_D$ (use magnitudes). The maximum equilibrium depletion width occurs at ${\varphi }_s=2{\varphi }_F$: W_T=\left[\frac{4K_S\varepsilon_0\phi_F}{qN_A}\right]^{1/2}\tag{16.16} Fig. 16.9 plots $W_T$ versus doping for Si at 300 K: it falls from a few microns at $10^{14}$ cm${}^{-3}$ to a few hundredths of a micron near $10^{18}$ cm${}^{-3}$.

16.3.2 Gate Voltage Relationship

The semiconductor results are functions of ${\varphi }_s$, but ${\varphi }_s$ is internal; what we control is $V_G$. In the ideal structure $V_G$ drops partly across the oxide and partly across the semiconductor: V_G=\Delta\phi_{semi}+\Delta\phi_{ox} \tag{16.17} Since $\varphi =0$ in the bulk, \Delta\phi_{semi}=\phi(0)=\phi_s \tag{16.18} In the oxide $d^2{\varphi }_{ox}/d{x}^2=0$, so ${\mathcal{E}}_{ox}$ is constant and \Delta\phi_{ox}=\mathcal{E}_{ox}\,x_o \tag{16.19-16.21} The boundary condition on normal displacement, $(D_{semi}-D_{ox}){|}_{O\text{-}S}=Q_{O\text{-}S}$, with $Q_{O\text{-}S}=0$ (idealization 3), gives K_S\varepsilon_0\mathcal{E}_s=K_O\varepsilon_0\mathcal{E}_{ox}\ \Rightarrow\ \mathcal{E}_{ox}=\frac{K_S}{K_O}\mathcal{E}_s \tag{16.24} \Delta\phi_{ox}=\frac{K_S}{K_O}x_o\mathcal{E}_s \tag{16.25} V_G=\phi_s+\frac{K_S}{K_O}x_o\mathcal{E}_s \tag{16.26} Note $K_S/K_O=11.8/3.9\approx 3$: the oxide field is about three times the surface field in silicon (band diagrams in this chapter should show this slope ratio). In delta-depletion, (16.12) and (16.15) give \mathcal{E}_s=\left[\frac{2qN_A\phi_s}{K_S\varepsilon_0}\right]^{1/2} \tag{16.27} V_G=\phi_s+\frac{K_S}{K_O}x_o\left[\frac{2qN_A\phi_s}{K_S\varepsilon_0}\right]^{1/2}\quad(0\le\phi_s\le2\phi_F) \tag{16.28} This relation is applied only to depletion biases (in delta-depletion ${\varphi }_s=0$ for all accumulation and $2{\varphi }_F$ for all inversion biases).

What Fig. 16.10 teaches. ${\varphi }_s$ changes rapidly with $V_G$ in depletion, but in accumulation (${\varphi }_s<0$) or inversion (${\varphi }_s>2{\varphi }_F$) a large change in $V_G$ produces only a small change in ${\varphi }_s$. There, changes in $V_G$ drop almost entirely across the oxide (the semiconductor is a stiff spring that will not budge). In depletion the voltage divides between oxide and semiconductor. The depletion region spans only about a volt, so the semiconductor changes character over a narrow voltage range.

Exercise 16.3

Problem. $T=300$ K, $x_o=0.1\mu$m, $N_A=10^{15}$ cm${}^{-3}$. Compute (a) ${\varphi }_F$ in $kT/q$ and volts, (b) $W$ when ${\varphi }_s={\varphi }_F$, (c) ${\mathcal{E}}_s$ when ${\varphi }_s={\varphi }_F$, (d) $V_G$ when ${\varphi }_s={\varphi }_F$.

Solution.

(a) $\frac{{\varphi }_F}{kT/q}=\ln \frac{N_A}{n_i}=\ln \frac{10^{15}}{10^{10}}=11.51$ ${\varphi }_F=(11.51)(0.0259)=0.298\text{V}$ (b) $W={\left[\frac{2K_S{\epsilon }_0{\varphi }_F}{q{N}_A}\right]}^{1/2}={\left[\frac{2(11.8)(8.85\times 10^{-14})(0.298)}{(1.6\times 10^{-19})(10^{15})}\right]}^{1/2}=6.24\times 10^{-5}\text{cm}=0.624\mu \text{m}$ (c) From (16.12) at $x=0$: ${\mathcal{E}}_s=\frac{q{N}_A}{K_S{\epsilon }_0}W=\frac{(1.6\times 10^{-19})(10^{15})(6.24\times 10^{-5})}{(11.8)(8.85\times 10^{-14})}=9.56\times 10^3\text{V/cm}$ (d) From (16.26): $V_G={\varphi }_F+\frac{K_S}{K_O}{x}_o{\mathcal{E}}_s=0.298+\frac{(11.8)(10^{-5})(9.56\times 10^3)}{3.9}=0.298+0.289=0.587\text{V}$

Comments. In $kT/q$ units $|{\varphi }_F|$ typically lies between 9 and 18. For nondegenerate MOS dopings $|{\varphi }_F|<0.56$ V (half the gap). $W<W_T$, as required. The surprise is the large surface field, $\sim 10^4$ V/cm. The parameters equal those of Fig. 16.10, and the result agrees with that plot.

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16.4 Capacitance-Voltage Characteristics

With d.c. current blocked, the MOS-C’s main observable is capacitance, which depends on the gate voltage. The $C$-$V$ curve is a “picture window” into the device and is routinely monitored during fabrication.

Measurement. The sample is on a probe station in a light-tight box, connected by shielded cables to a $C$-$V$ meter (Subsection 7.2.3, Fig. 7.6). The meter superimposes a small a.c. signal (typically $\le 15$ mV rms, usually 1 MHz) on a slowly varied d.c. voltage and measures the a.c. current. Output is displayed and plotted by computer. More sophisticated systems combine 1 MHz and low-frequency (quasistatic) measurements (Fig. 16.11a). The words low-frequency and high-frequency originally referred to the a.c. signal frequency.

16.4.1 Theory and Analysis

Qualitative theory

Fig. 16.11(b) shows measured high- and low-frequency curves. To understand them, track how the a.c. signal moves charge in an n-type MOS-C as the d.c. bias goes from accumulation through depletion to inversion (Fig. 16.12).

Accumulation. Majority carriers pile up at the interface and equilibrate in $10^{-10}$ to $10^{-13}$ s, so at 1 MHz or lower the device follows the signal quasistatically: the a.c. signal adds or subtracts a small $\Delta Q$ close to the two faces of the oxide, like an ordinary parallel-plate capacitor, at any frequency: C(\text{acc})=C_o=\frac{K_O\varepsilon_0A_G}{x_o} \tag{16.29}

Depletion. The d.c. state is $-Q$ on the gate and $+Q$ of depletion charge. Only majority carriers move, so the depletion width fluctuates quasistatically about its d.c. value at all frequencies. Dropping the stationary charge leaves small fluctuating charges across a double-layer insulator: two capacitors in series, the oxide and the depletion layer: C_o=\frac{K_O\varepsilon_0A_G}{x_o},\qquad C_s=\frac{K_S\varepsilon_0A_G}{W}\tag{16.30} C(\text{depl})=\frac{C_oC_s}{C_o+C_s}=\frac{C_o}{1+\dfrac{K_OW}{K_Sx_o}}\tag{16.31} Since $W$ grows with depletion bias, $C$ falls from flat band to the onset of inversion.

Inversion. The d.c. depletion width is near its maximum $W_T$. How does the a.c. charge respond? Two extremes:

• Very low frequency ($\omega \to 0$): minority carriers can be generated or annihilated in step with the signal, so the response is a succession of d.c. states, with charge added at the oxide-semiconductor edge only (Fig. 16.12c). Single-layer insulator: C(\text{inv})\approx C_o\quad(\omega\to0)\tag{16.32}
• Very high frequency ($\omega \to \infty$): sluggish generation-recombination cannot supply minority carriers, so the inversion layer charge stays fixed and the depletion width fluctuates about $W_T$ (Fig. 16.12d). Again two capacitors in series: C(\text{inv})=\frac{C_o}{1+\dfrac{K_OW_T}{K_Sx_o}}\quad(\omega\to\infty)\tag{16.33} This is the minimum capacitance, since $W_T$ is the largest equilibrium $W$. At intermediate frequencies a partial response gives a value in between.

Overall picture. $C\approx C_o$ in accumulation; $C$ falls through depletion; $C\approx C_o$ in inversion for $\omega \to 0$, or $C_{min}$ for $\omega \to \infty$. For an n-type device accumulation is at positive $V_G$, inversion at negative $V_G$, and the depletion region spans about a volt. This agrees with Fig. 16.11(b).

Exercise 16.4

Problem. Complete the table using the ideal $C$-$V$ curve (points a-g) and block charge diagrams (1-5) of Fig. E16.4 (n-bulk device).

Solution. (From the book’s answer line.)

Bias condition	Capacitance point	Charge diagram
Accumulation	g	3
Depletion	e	1
Inversion	a, b or c	4
Flat band	f	2
Depl/inv transition	d	5

Reasoning: accumulation has $C=C_o$ (top plateau, positive-voltage side) with electrons at the interface (diagram 3). Flat band is the knee between plateau and falling region (diagram 2, no charge). Depletion is the falling part (diagram 1, donor ions only). The transition is where depletion has just reached $W_T$ (diagram 5). Inversion points lie on the negative-voltage side with a hole layer (diagram 4).

Delta-depletion analysis

In delta-depletion the accumulation and inversion layers are $\delta$-functions at the interface, so C=C_o\quad\text{(accumulation)}\tag{16.34a} C=\frac{C_o}{1+K_OW/K_Sx_o}\quad\text{(depletion)}\tag{16.34b} C=C_o\quad\text{(inversion, }\omega\to0)\tag{16.34c} C=\frac{C_o}{1+K_OW_T/K_Sx_o}\quad\text{(inversion, }\omega\to\infty)\tag{16.34d}

To express $W$ in terms of $V_G$, invert (16.28). Write $a\equiv K_S{x}_o/K_O$ and $k\equiv q{N}_A/(2K_S{\epsilon }_0)$. Then ${\varphi }_s=k{W}^2$ and ${\mathcal{E}}_s=q{N}_{A}W/K_S{\epsilon }_0=2kW$, so $V_G=k{W}^2+a\cdot 2kW$ $V_G+k{a}^2=k(W+a{)}^2\text{(complete the square)}$ $W=a\left[\sqrt{1+\frac{V_G}{k{a}^2}}-1\right]$ Defining $V_{\delta }\equiv k{a}^2$: W=\frac{K_S}{K_O}x_o\left[\sqrt{1+\frac{V_G}{V_\delta}}-1\right]\tag{16.35} V_\delta=\frac{qN_AK_Sx_o^2}{2\varepsilon_0K_O^2}\quad\text{(p-bulk; }N_A\to-N_D\text{ for n-bulk)}\tag{16.36} Substituting (16.35) into (16.34b), $1+\frac{K_{O}W}{K_S{x}_o}=\sqrt{1+V_G/V_{\delta }}$, so C=\frac{C_o}{\sqrt{1+V_G/V_\delta}}\quad\text{(depletion biases)}\tag{16.37} Fig. 16.13 shows a delta-depletion set ($x_o=0.1\mu$m, $N_D=10^{15}$ cm${}^{-3}$).

16.4.2 Computations and Observations

Exact computations

The delta-depletion curves are crude near the transition points (accumulation to depletion, depletion to inversion). Accurate curves use the exact-charge analysis (Appendix C). Fig. 16.14 to 16.16 show the trends:

• Doping (Fig. 16.14): higher doping gives a higher high-frequency inversion capacitance and a much wider depletion bias region. At very high doping the semiconductor looks like a metal and the capacitance approaches a bias-independent $C_o$.
• Oxide thickness (Fig. 16.15): thicker oxide gives a wider depletion region (proportionally more voltage drops across the oxide) and changes the high-frequency inversion capacitance.
• Temperature (Fig. 16.16): inversion capacitance is moderately sensitive; depletion capacitance is nearly insensitive.

Exercise 16.5 (computer)

Problem. (a) Write a MATLAB program using the exact-charge relations to compute and plot low-frequency $C/C_o$ vs $V_G$, with $U={\varphi }_s/(kT/q)$ stepped by 1 from $U_F-21$ to $U_F+21$; $K_S=11.8$, $K_O=3.9$, $T=300$ K; inputs only $N_A$ and $x_o$. Use $N_A=10^{15}$ cm${}^{-3}$ and $x_o=0.1,0.2,0.3\mu$m. (b) Do the same for high frequency with $x_o=0.1\mu$m and three dopings.

Solution and logic. I derive the needed Appendix B/C results (p-type) so the program is self-contained. Define $U=q\varphi /kT$, $U_F=q{\varphi }_F/kT$, and the intrinsic Debye length $L_D=\sqrt{K_S{\epsilon }_{0}kT/(2q^2{n}_i)}=2.91\times 10^{-3}$ cm. Then $p=n_i{e}^{U_F-U},n=n_i{e}^{U-U_F},N_A=n_i(e^{U_F}-e^{-U_F})$ $\rho =q{n}_i\left[e^{U_F-U}-e^{U-U_F}-e^{U_F}+e^{-U_F}\right]$ Poisson gives $\frac{d^{2}U}{d{x}^2}=-\frac{1}{2L_D^2}\left[e^{U_F}(e^{-U}-1)-e^{-U_F}(e^U-1)\right]$ Multiply by $dU/dx$ and integrate from the bulk ($U=0$, $dU/dx=0$) to $U$: ${\left(\frac{dU}{dx}\right)}^2=\frac{1}{L_D^2}\left[e^{U_F}(e^{-U}+U-1)+e^{-U_F}(e^U-U-1)\right]$ So the surface field is ${\mathcal{E}}_s=\mathrm{sgn}(U_s)\frac{kT}{q}\frac{F(U_s,U_F)}{\sqrt{2}{L}_D}$ with $F(U,U_F)=\sqrt{2\left[e^{U_F}(e^{-U}+U-1)+e^{-U_F}(e^U-U-1)\right]}$ With (16.26): $V_G=\frac{kT}{q}\left[U_s+\mathrm{sgn}(U_s)\frac{K_S}{K_O}\frac{x_o}{\sqrt{2}{L}_D}F(U_s,U_F)\right]$ Low-frequency capacitance. $C_s=K_S{\epsilon }_{0}A|d{\mathcal{E}}_s/d{\varphi }_s|=\frac{K_S{\epsilon }_{0}A}{\sqrt{2}{L}_D}|F^{\prime }|$, with $F^{\prime }=\frac{dF}{dU}=\frac{e^{U_F}(1-e^{-U})+e^{-U_F}(e^U-1)}{F}$ Since $C=C_o{C}_s/(C_o+C_s)$, $\frac{C}{C_o}={\left[1+\frac{K_O}{K_S}\frac{\sqrt{2}{L}_D}{x_o}\frac{1}{|F^{\prime }|}\right]}^{-1}$ (At $U=0$, $F^{\prime }\to \sqrt{2\cosh U_F}$; the program avoids $U=0$ exactly.)

High frequency. Minority carriers cannot follow, so deep-inversion capacitance saturates at a value set by an effective depletion width, $C/C_o=[1+(K_O/K_S)(W_{eff}/x_o){]}^{-1}$. A practical program uses the low-frequency curve for $U\le 2U_F$ (identical to HF in depletion) and beyond that the smaller of $C_{LF}$ and $K_S{\epsilon }_{0}A/W_{eff}$, with $W_{eff}$ from the approximate expression of Problem 16.17. The book’s MOS_CV file (Appendix M) does the exact, more intensive HF calculation; this version is an approximation.

% Low-frequency MOS-C C-V, p-type, exact-charge theory
kTq=0.0259; ni=1e10; Ks=11.8; Ko=3.9; e0=8.85e-14; q=1.6e-19;
NA=1e15;                              % input doping
LD=sqrt(Ks*e0*kTq/(2*q*ni));          % intrinsic Debye length (cm)
UF=log(NA/ni);
U=(UF-21):1:(UF+21);
U(abs(U)<1e-6)=1e-6;                  % avoid U=0 exactly
F =@(U) sqrt(2*(exp(UF)*(exp(-U)+U-1)+exp(-UF)*(exp(U)-U-1)));
Fp=@(U) (exp(UF)*(1-exp(-U))+exp(-UF)*(exp(U)-1))./F(U);
xos=[0.1 0.2 0.3]*1e-4;               % oxide thicknesses (cm)
figure; hold on
for xo=xos
  VG = kTq*(U + sign(U).*(Ks/Ko)*xo/(sqrt(2)*LD).*F(U));
  CC = 1./(1+(Ko/Ks)*sqrt(2)*LD/xo./abs(Fp(U)));   % C/Co
  plot(VG,CC)
end
xlabel('V_G (volts)'); ylabel('C/C_o'); grid on
legend('0.1 um','0.2 um','0.3 um')

Sample numbers (computed with this logic; $N_A=10^{15}$, $x_o=0.1\mu$m): $U=U_F=11.51$ gives $V_G=0.575$ V and $C/C_o=0.337$; $U=2U_F=23.03$ gives $V_G=1.005$ V; $U=U_F+21$ gives $V_G\approx 10.6$ V with $C/C_o\approx 0.995$ (back to $C_o$). Thicker oxide shifts the transition to larger $|V_G|$, as in Fig. 16.15.

Practical observations

• What is “low” or “high” frequency? Surprisingly, a 100 Hz signal does not give low-frequency data. With modern long lifetimes and low generation rates, even 10 Hz (the practical limit of bridge measurements) yields high-frequency curves. A true low-frequency curve needs the quasistatic technique: a slow (10-100 mV/s) linear ramp is applied to the gate, the gate current is monitored, and the displacement current is proportional to the low-frequency capacitance.
• High-frequency limit: one cannot let $\omega \to \infty$. At high frequency the bulk resistance lowers the observed capacitance, and at $\ge 1$ GHz majority carrier response time matters. The near-universal measurement frequency is 1 MHz.
• Ramp caution and deep depletion. If the d.c. voltage is ramped from accumulation into inversion (Fig. 16.17), the inversion part of the HF curve is not plotted correctly, even at the slowest ramp. In accumulation and depletion only majority carriers are needed, so charge follows the ramp. Entering inversion, minority carriers must be created in the near-surface region. Generation is sluggish, so the semiconductor is driven out of equilibrium. To balance the added gate charge, the depletion width exceeds $W_T$ (Fig. 16.18a). This nonequilibrium state, with a deficit of minority carriers and $W>W_T$, is deep depletion. It explains the reduced capacitance, and the faster the ramp the wider $W$. The limit is total deep depletion, with no minority carriers at all. It looks like simple depletion with wider $W$, so by (16.37): C=\frac{C_o}{\sqrt{1+V_G/V_\delta}}\quad(V_G>V_T\ \text{p-type};\ V_G<V_T\ \text{n-type})\tag{16.38} This agrees well with experiment (the 2.6 V/s curve in Fig. 16.17). To record the true HF inversion capacitance, stop the ramp and let the device equilibrate, or sweep slowly backward from inversion to accumulation.

Deep depletion is central to DRAMs (deeply depleted MOS capacitors store the bits) and CCD imagers (optically generated charge is held in partially deep-depleted wells under an array of gates).

Exercise 16.6

Problem. The $C$-$V$ curve of Fig. E16.6 was recorded as follows: d.c. bias changed very slowly from point 1 to point 2; at point 2 the sweep rate was substantially increased; at point 3 the sweep was stopped and $C$ decayed to point 4. Explain.

Solution. From 1 to 2 the sweep is so slow that the semiconductor equilibrates at each point, so the standard HF $C$-$V$ curve is traced. At point 2 the faster ramp gives minority carriers no time to be generated, so the device enters deep depletion: $W$ exceeds $W_T$ and $C$ drops below the equilibrium HF minimum. When the sweep stops at 3, minority carriers are generated in the near-surface region and add to the inversion layer, the depletion width shrinks, and $C$ rises from 3 back to 4, the equilibrium HF value.

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16.5 Summary and Concluding Comments

The chapter introduced MOS terminology, concepts, visualization aids and analytical procedures. The ideal MOS-C is both a teaching tool and a reference for more complex real structures (Chapter 18 relaxes some idealizations).

• Qualitative picture (energy bands and block charge). Accumulation is the pileup of majority carriers at the interface. Flat band is no band bending, equivalently no semiconductor charge. Depletion is repulsion of majority carriers, leaving uncompensated ionized impurities. Inversion is the pileup of minority carriers at the interface.
• Terminology note. Some texts split the depletion region: “depletion” only for $0<{\varphi }_s<{\varphi }_F$, weak inversion for ${\varphi }_F<{\varphi }_s<2{\varphi }_F$, and strong inversion for what is called inversion here.
• Quantitative. Poisson’s equation gives $\rho$, $\mathcal{E}$, $\varphi$. The first-order solution uses the depletion approximation and $\delta$-function carrier layers; the exact one is in Appendix B.
• $C$-$V$ characteristics were modeled in the low- and high-frequency limits, examined for parameter dependence, and the practical meaning of “low” and “high” was clarified. Deep depletion occurs when the MOS-C cannot equilibrate under inversion bias: a nonequilibrium state with a minority-carrier deficit and $W>W_T$.

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