part12

Part III: Field Effect Devices (Opener)

Parts I and II of the book built the physics of semiconductors and of junctions. Part III now turns to a different way of controlling current: instead of injecting carriers across a junction (as in a BJT), we reach into a slab of semiconductor with an electric field and squeeze or widen the conducting path. Think of a garden hose and your foot. The hose is the semiconductor, the water is current, and your foot, pressing from the outside without entering the hose, is the gate. This is the entire idea of the field effect, and every MOSFET in every processor you have ever used is a refinement of it.

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Chapter 15: Field Effect Introduction: The J-FET and MESFET

15.1 General Introduction

The idea is older than the transistor you know

The field effect is the modulation of the conductivity of a semiconductor by an electric field applied normal (perpendicular) to the semiconductor surface.

Here is the surprising history. Field effect transistors predate the bipolar junction transistor by about 20 years. In patents filed in the 1920s and 1930s, J. E. Lilienfeld (USA) and O. Heil (Germany) independently conceived the structure of Fig. 15.1: a semiconductor (Cu${}_2$S) bar with ohmic contacts A and B at the ends and a metal plate (aluminum) lying over it. A voltage on the plate changes the conductance of the bar underneath, and therefore the current between A and B.

Figure 15.1 (described): Lilienfeld’s idealization. A slab of semiconductor with two metal end contacts A and B, and a metal plate C resting on top of the slab. The plate-to-semiconductor voltage modulates the conductance between A and B.

Why did it not work then? It was an idea ahead of its time. Good semiconductor material did not exist, and the technology was immature. Practical field-effect devices had to wait for the success of the bipolar transistor in the late 1940s and early 1950s.

A timeline of field-effect devices

Year	Event
1920s-30s	Lilienfeld and Heil propose the field-effect transistor
1952	Shockley proposes and analyzes the junction FET (J-FET)
1953	Dacey and Ross build operational J-FETs
1960	Kahng and Atalla report the planar MOSFET (thermal SiO${}_2$ gate insulator, inversion-layer channel)
1964	Commercial MOSFETs from Fairchild and RCA
late 1960s	Dennard invents the one-transistor DRAM cell
early 1970s	Charge-coupled device (CCD) introduced
1980s	CMOS becomes the integrated-circuit technology of choice
later	MODFET (modulation-doped FET), fastest three-terminal semiconductor device

The J-FET. Shockley’s J-FET replaced the Lilienfeld metal plate by $pn$ junctions (Fig. 15.2). The end contacts A and B are renamed source and drain, and the field-effect electrode is the gate. Here it is the depletion regions of the $pn$ junctions that directly modulate the conductance between source and drain.

The MOSFET. The planar MOSFET (Fig. 15.3) has a thermally grown SiO${}_2$ gate insulator, a surface-inversion channel, and source/drain islands doped opposite to the substrate.

The DRAM cell. A 1-T DRAM cell (Fig. 15.4) is a storage element (a capacitor or $pn$ junction) plus a MOSFET acting as a switch. A review article quoted in the book says the 1-T DRAM cell “is now the most abundant man-made object on this planet earth.” Fig. 15.4 shows a planar cell: a polysilicon capacitor plate, an access transistor with gate oxide, an $n^{+}$ drain, field oxide, and a field implant in $p$-silicon.

The CCD. A CCD can be viewed as a MOSFET with a segmented gate (Fig. 15.5, three-phase gates $P_1,P_2,P_3$, input and output gates and diodes on $p$-silicon). Biasing the gates in sequence pushes stored charge packets along the surface channel to the output. The image sensor in a camcorder is a CCD with a two-dimensional gate array: charge is generated in proportion to the optical image, then shifted out and converted to an electrical signal.

CMOS. Complementary MOS puts both $n$-channel (electron-carrying) and $p$-channel (hole-carrying) MOSFETs on the same chip. Fig. 15.6 shows a cut-away CMOS inverter: an $n$-channel MOSFET (with $n^{+}$ source/drain in a $p$ region) beside a $p$-channel MOSFET ($p^{+}$ source/drain in an $n$ well), with thermal and CVD SiO${}_2$ and Al interconnect. CMOS won in the 1980s because of low power dissipation. The change was evolutionary: CMOS existed in the 1960s and was even mass produced in LED watches by 1972.

The MODFET. GaAs has better electron transport than Si but lacks a good native insulator, and deposited insulators on GaAs give poor devices. Molecular beam epitaxy (MBE) can grow lattice-matched layers of different semiconductors. The alloy AlGaAs has a larger band gap than GaAs and takes over the role of “insulator.” In the MODFET (Fig. 15.7) an $n$-AlGaAs layer sits on undoped GaAs, and a two-dimensional electron gas (2 DEG) forms at the interface. It is touted as the fastest three-terminal semiconductor device and is used at high frequencies.

Roadmap of Part III (Part III is five chapters)

• Chapter 15 (this chapter): the J-FET and the closely related MESFET. They act as conceptual bridges between the junction devices of Part II and the “pure” field-effect devices. They also serve as a first pass through terminology and analytical methods.
• Chapters 16-17: MOS fundamentals. The MOS capacitor (MOS-C) is the structural heart of all MOS devices. Chapter 16 covers the ideal MOS-C and its $C$-$V$ behavior. Chapter 17 covers the long-channel enhancement-mode MOSFET.
• Chapters 18-19: deviations from the ideal (Ch. 18) and small-dimension effects plus a survey of other FETs (Ch. 19).

Intuition check. Why is the J-FET a “bridge”? It still contains $pn$ junctions (like Part II) but the current is controlled by a field acting across a depletion region (like Part III).

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15.2 J-FET

15.2.1 Introduction

The cross section of the basic structure is Fig. 15.8. A central $n$ region (the channel) connects the source (S) and drain (D). Heavily doped $p^{+}$ gates sit on top and bottom (both labelled G). A gate voltage changes the $pn$-junction depletion widths and the associated electric field normal to the semiconductor surface. The width changes modulate the conductance between the ohmic source and drain contacts.

Why “unipolar”? The J-FET was first called the unipolar transistor. Normal operation involves only one type of carrier, here electrons in the $n$ region moving from source to drain. (A BJT needs both electrons and holes.)

Naming the terminals.

• Source: carriers enter the semiconductor from the external circuit here.
• Drain: carriers leave the semiconductor (“are drained”) here.
• Gate: gets its name from its controlling, “gating” action.

The modern epilayer J-FET (Fig. 15.9) has an $n$-epi layer on a $p$-Si substrate, $p^{+}$ gate diffusions, $n^{+}$ source and drain contacts, SiO${}_2$ passivation and isolation. Its appearance differs, but it is functionally equivalent to Shockley’s structure.

15.2.2 Qualitative Theory of Operation

Standard biasing. For the symmetrical Shockley structure (Fig. 15.10) with the top and bottom gates tied together:

$V_G\le 0,V_D\ge 0$

• $V_G\le 0$ means the $p^{+}$-$n$ junctions are always zero or reverse biased, so the gate draws almost no current.
• $V_D\ge 0$ pulls electrons from source to drain, consistent with the names S and D.

Our plan: change the terminal voltages one at a time and look inside the device.

Case 1: $V_G=0$, raise $V_D$ from 0 (Fig. 15.11)

(a) Equilibrium, $V_D=0$. The device is in thermal equilibrium. All one sees are small depletion regions around the two $p^{+}$-$n$ junctions, extending mainly into the lightly doped $n$ side.

(b) Small $V_D$. A current $I_D$ flows through the nondepleted $n$ region between the two junctions. That conducting region is the channel. For small $V_D$ it looks like a plain resistor, so $I_D$ varies linearly with $V_D$ (Fig. 15.12a).

(c)-(d) Moderate $V_D$ (a few tenths of a volt and up). Imagine $V_D=5$ V, source grounded. Along the channel the potential must pass through 1, 2, 3, 4 V going from source to drain. The $p^{+}$ gate sides are held at 0 V. So the junction reverse bias grows from the source end toward the drain end. The depletion regions widen progressively along the channel and the channel funnels down (Fig. 15.11d). This is still a resistor, but no longer a simple one: less conducting volume means more resistance, so the slope of the $I_D$-$V_D$ curve decreases (Fig. 15.12b).

Analogy. A river flowing between two banks that slowly squeeze inward. The more the banks pinch near the end, the harder it is to push additional water through.

(e) Pinch-off. Keep raising $V_D$ and the top and bottom depletion regions finally touch near the drain (Fig. 15.11e). This is pinch-off: complete depletion of the channel at one point. The slope of $I_D$-$V_D$ becomes approximately zero (Fig. 15.12c). The drain voltage at which this happens is named $V_{Dsat}$. For $V_D>V_{Dsat}$ the characteristic saturates at $I_{Dsat}$.

(f) Post pinch-off, $V_D>V_{Dsat}$. A short depleted section of length $\Delta L$ appears next to the drain.

Two paradoxes that confuse everyone

Paradox 1: Doesn’t pinch-off kill the current? Suppose $I_D=0$ at pinch-off. Then no current flows anywhere in the channel, so there is no voltage drop along it, so the channel potential is zero everywhere. Then the $pn$ junctions are zero biased and the channel is wide open, contradicting the assumption of a pinched channel. So current must flow to create and maintain pinch-off.

The hidden misconception is that a large current cannot pass through a depletion region. Depletion regions are not empty of carriers. Their carrier densities are merely small relative to the doping and can still reach $\sim 10^{12}$ cm${}^{-3}$ or more. Large currents pass through depletion regions all the time: the forward-biased diode and both depletion regions of a BJT.

Paradox 2: Why doesn’t $I_D$ change for $V_D>V_{Dsat}$? As $V_D$ rises above $V_{Dsat}$, a section $\Delta L$ next to the drain becomes depleted. The voltage on its drain side is $V_D$ and on its source side is $V_{Dsat}$. So the extra voltage $V_D-V_{Dsat}$ is dropped across the depleted section. If $\Delta L\ll L$ (the usual case), the source-to-pinch-off portion has the same shape and the same end-point voltages (0 and $V_{Dsat}$) as at the onset of saturation. Same shape plus same applied voltage means same current. So $I_D$ stays about constant.

If $\Delta L$ is comparable to $L$, the same $V_{Dsat}$ appears across a shorter section $L-\Delta L$, and $I_D$ rises noticeably with $V_D$. This is a short-channel effect (channel-length modulation).

The waterfall analogy (Fig. 15.13). The flow over a waterfall is set not by the height of the fall but by the flow rate in the rapids leading to it. Two falls of different heights fed by identical rapids deliver identical flow. Rapids = source side of the channel. Fall = the pinched $\Delta L$ section. Height of the fall = the potential drop $V_D-V_{Dsat}$.

Case 2: $V_G<0$ (Fig. 15.14)

Similar to $V_G=0$ with three modifications:

1. The junctions are reverse biased even at $V_D=0$, so depletion regions are wider and the channel is thinner. Channel resistance is higher and the linear-region slope is smaller (Fig. 15.14a).
2. A thinner channel pinches off at a smaller drain bias, so $V_{Dsat}$ and $I_{Dsat}$ are smaller than for $V_G=0$ (Fig. 15.14b).
3. For sufficiently negative $V_G$ the entire channel is depleted even at $V_D=0$ (Fig. 15.14c). The gate voltage where this first happens is the pinch-off gate voltage, $V_G=V_P$. For $V_G\le V_P$, $I_D=0$ for all drain biases.

Footnote from the text: at very large $V_D$ the junctions near the drain break down and $I_D$ rises abruptly. This is omitted from all sketched characteristics.

15.2.3 Quantitative $I_D$-$V_D$ Relationships

Wanted: $I_D=I_D(V_D,V_G)$.

Device specification (Fig. 15.15).

• $y$-axis runs down the channel from source ($y=0$) to drain ($y=L$).
• $x$-axis is normal to the $p^{+}$-$n$ metallurgical junctions.
• $L$ = channel length, $Z$ = lateral width, $2a$ = separation between the top and bottom metallurgical junctions.
• $V(y)$ = channel potential at $y$. $W(y)=W_{top}(y)=W_{bottom}(y)$ = depletion width, lying almost entirely in the $n$ side because the junctions are $p^{+}$-$n$.

Basic assumptions.

1. $p^{+}$-$n$ step junctions, uniformly doped $n$ region with donor concentration $N_D$.
2. Structure symmetric about the plane $x=a$ (the same $V_G$ on both gates).
3. Current flows only in the nondepleted $n$ region, exclusively in the $y$ direction.
4. $W(y)$ can reach at least $a$ without junction breakdown.
5. $L\gg a$.

Valid range: $0\le V_D\le V_{Dsat}$ and $0\ge V_G\ge V_P$.

Step 1: Current density in the channel

The general electron current density is

J_N = q\mu_n n\,\mathcal{E} + qD_N\nabla n \tag{15.1}

Inside the channel $n\approx N_D$ (uniform), so the diffusion term is negligible, and the field is ${\mathcal{E}}_y=-dV/dy$:

J_{N_y}=q\mu_n N_D\,\mathcal{E}_y=-q\mu_n N_D\frac{dV}{dy} \tag{15.2}

Step 2: Integrate over the cross section

No carriers are created or lost, so the current through any cross section equals $I_D$. $I_D$ is defined positive in the $-y$ direction, hence the minus sign. Using the symmetry about $x=a$ (two halves, $x$ from $W$ to $a$):

I_D=-\int J_{N_y}\,dA = -Z\int_{W(y)}^{2a-W(y)}J_{N_y}\,dx = 2Zq\mu_nN_D\frac{dV}{dy}\int_{W(y)}^{a}dx \tag{15.3a}

I_D=2qZ\mu_nN_D\,[a-W(y)]\frac{dV}{dy} \tag{15.3b}

Step 3: Separate variables and integrate over the channel length

$I_D$ is independent of $y$, so write $I_{D}dy=2qZ{\mu }_n{N}_D[a-W]dV$ and integrate from $y=0$ ($V=0$) to $y=L$ ($V=V_D$):

\int_0^L I_D\,dy = I_DL = 2qZ\mu_nN_D\int_{V(0)=0}^{V_D}[a-W(V)]\,dV \tag{15.4}

I_D=\frac{2qZ\mu_nN_Da}{L}\int_0^{V_D}\left[1-\frac{W(V)}{a}\right]dV \tag{15.5}

Step 4: The gradual channel approximation

The true electrostatics are two-dimensional (Poisson in $x$ and $y$). Because $L\gg a$, variations along $y$ are far more gradual than those along $x$. The gradual channel approximation neglects $\partial /\partial y$ in Poisson’s equation, giving a one-dimensional $x$-direction solution at each $y$. Thus, using the one-sided step-junction result (Eq. 5.38),

W(V)=\left[\frac{2K_S\varepsilon_0}{qN_D}\,(V_{bi}-V_A)\right]^{1/2}=\left[\frac{2K_S\varepsilon_0}{qN_D}\,(V_{bi}+V-V_G)\right]^{1/2} \tag{15.6}

Here $V_A=V_G-V(y)$ is the applied voltage across the junction at $y$ (negative means reverse bias).

Step 5: Pinch-off voltage in terms of device parameters

$W\to a$ when $V_D=0$ and $V_G=V_P$ (that is how $V_P$ is defined). Putting $V=0$, $V_G=V_P$ in (15.6):

a=\left[\frac{2K_S\varepsilon_0}{qN_D}(V_{bi}-V_P)\right]^{1/2} \tag{15.7}

Equivalently $V_P=V_{bi}-\frac{q{N}_D{a}^2}{2K_S{\epsilon }_0}$. Dividing (15.6) by (15.7):

\frac{W(V)}{a}=\left[\frac{V_{bi}+V-V_G}{V_{bi}-V_P}\right]^{1/2} \tag{15.8}

Step 6: Do the integral

Let $c\equiv V_{bi}-V_P$. Substitute (15.8) into (15.5):

${\int }_0^{V_D}\left[1-\frac{(V_{bi}-V_G+V{)}^{1/2}}{c^{1/2}}\right]dV=V_D-\frac{1}{c^{1/2}}\cdot \frac{2}{3}[(V_{bi}-V_G+V{)}^{3/2}{]}_0^{V_D}$

$=V_D-\frac{2}{3}\frac{(V_D+V_{bi}-V_G{)}^{3/2}-(V_{bi}-V_G{)}^{3/2}}{(V_{bi}-V_P{)}^{1/2}}$

So, with $G_0\equiv 2qZ{\mu }_n{N}_{D}a/L$:

\boxed{I_D=G_0\left\{V_D-\frac{2}{3}\,\frac{(V_D+V_{bi}-V_G)^{3/2}-(V_{bi}-V_G)^{3/2}}{(V_{bi}-V_P)^{1/2}}\right\},\quad 0\le V_D\le V_{Dsat},\ V_P\le V_G\le 0} \tag{15.9}

$G_0$ has a clear physical meaning: it is the channel conductance you would have if there were no depletion regions (full thickness $2a$, so $G=q{\mu }_n{N}_D(2a)Z/L$).

Check: for small $V_D$ expand $(V_D+x{)}^{3/2}\approx x^{3/2}+\frac{3}{2}{x}^{1/2}{V}_D$ with $x=V_{bi}-V_G$, giving $I_D\approx G_0{V}_D\left[1-\sqrt{(V_{bi}-V_G)/(V_{bi}-V_P)}\right]$. That is a resistor whose conductance shrinks as $V_G$ becomes more negative, and vanishes at $V_G=V_P$. This is the linear region of Fig. 15.14a.

Step 7: Saturation

Equation (15.9) is valid only below pinch-off. If you stubbornly plug in $V_D>V_{Dsat}$, the computed $I_D$ actually decreases. Since $I_D$ is really about constant above pinch-off, model it as

I_D\big|_{V_D>V_{Dsat}}=I_{Dsat}=I_D\big|_{V_D=V_{Dsat}} \tag{15.10a, b}

At the drain end pinch-off means $W\to a$ at $V(L)=V_{Dsat}$. From (15.6):

a=\left[\frac{2K_S\varepsilon_0}{qN_D}(V_{bi}+V_{Dsat}-V_G)\right]^{1/2} \tag{15.11}

Comparing with (15.7), $V_{bi}+V_{Dsat}-V_G=V_{bi}-V_P$, so

\boxed{V_{Dsat}=V_G-V_P} \tag{15.12}

(Remember $V_P<0$, so $V_{Dsat}>0$ for $V_G\ge V_P$. At $V_G=V_P$, $V_{Dsat}=0$: no current. At $V_G=0$, $V_{Dsat}=|V_P|$.)

Substituting $V_D=V_G-V_P$ into (15.9): $(V_D+V_{bi}-V_G{)}^{3/2}=(V_{bi}-V_P{)}^{3/2}$, so

I_{Dsat}=G_0\left\{(V_G-V_P)-\frac{2}{3}(V_{bi}-V_P)\left[1-\left(\frac{V_{bi}-V_G}{V_{bi}-V_P}\right)^{3/2}\right]\right\} \tag{15.13}

where the bracket arises because $(V_{bi}-V_P{)}^{3/2}/(V_{bi}-V_P{)}^{1/2}=V_{bi}-V_P$ and $(V_{bi}-V_G{)}^{3/2}/(V_{bi}-V_P{)}^{1/2}=(V_{bi}-V_P){\left(\frac{V_{bi}-V_G}{V_{bi}-V_P}\right)}^{3/2}$.

Comparison with experiment. Fig. 15.16 plots normalized theory ($V_{bi}=1$ V, $V_P=-2.5$ V; $V_G=0,-0.5,-1.0,-1.5,-2.0$ V; the locus $I_{Dsat}$ vs. $V_{Dsat}$ is a dashed line through the knee of every curve). Fig. 15.17 shows measured curves for a TI 2N3823 $n$-channel J-FET ($I_D$ up to 5 mA, $V_D$ to 5 V). Theory models experiment reasonably well. Better agreement follows from including the series resistance of the regions between the active channel and the contacts (Fig. 15.18, $R_S$ and $R_D$; see Exercise 15.3).

Square-law approximation. Most J-FETs in saturation obey

I_{Dsat}=I_{D0}\left(1-\frac{V_G}{V_P}\right)^2,\qquad I_{D0}=I_{Dsat}\big|_{V_G=0} \tag{15.14}

It looks completely different from (15.13) but gives similar numbers and is easier for first-order circuit work (device as a “black box”). Eq. (15.13) remains indispensable for studying dependence on temperature, doping, or other fundamental parameters.

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Exercise 15.1: Maximum half-width $a$

Problem. An $n$-channel Si J-FET has $N_D=10^{16}$ cm${}^{-3}$. At room temperature, find the maximum half-width $a$.

Solution. For saturating characteristics the channel must pinch off before the junctions break down, i.e. $a\le W_{BR}$ (depletion width at the breakdown voltage). From Fig. 6.11, $V_{BR}\approx 55$ V for $N_D=10^{16}$ cm${}^{-3}$ $p^{+}$-$n$ junctions, and $V_{bi}=0.92$ V (from the Exercise 5.1 figure).

$a_{max}=W_{BR}={\left[\frac{2K_S{\epsilon }_0}{q{N}_D}(V_{bi}+V_{BR})\right]}^{1/2}$

$={\left[\frac{(2)(11.8)(8.85\times 10^{-14})}{(1.6\times 10^{-19})(10^{16})}(0.92+55)\right]}^{1/2}\text{cm}$

$={\left[7.30\times 10^{-8}\right]}^{1/2}\text{cm}=2.70\times 10^{-4}\text{cm}$

$\boxed{a_{max}=2.70\mu \text{m}}$

Exercise 15.2: Phenomenological versus square-law $I_{Dsat}/I_{D0}$

Problem. Plot $I_{Dsat}/I_{D0}$ vs. $V_G/V_P$ using (15.13) and (15.14) for $V_{bi}/V_P=-0.4$ (i.e. $V_{bi}=1$ V, $V_P=-2.5$ V). How does the comparison vary with $V_{bi}/V_P$?

Solution. Setting $V_G=0$ in (15.13):

$I_{D0}=G_0\left\{-V_P-\frac{2}{3}(V_{bi}-V_P)\left[1-{\left(\frac{V_{bi}}{V_{bi}-V_P}\right)}^{3/2}\right]\right\}$

Divide numerator and denominator of the ratio by $V_P$ (which is negative, but cancels in the ratio). Define $x=V_G/V_P$ and $z=V_{bi}/V_P$:

$\frac{I_{Dsat}}{I_{D0}}=\frac{(x-1)-\frac{2}{3}(z-1)\left[1-{\left(\frac{z-x}{z-1}\right)}^{3/2}\right]}{-1-\frac{2}{3}(z-1)\left[1-{\left(\frac{z}{z-1}\right)}^{3/2}\right]}$

The square-law ratio is simply

$\frac{I_{Dsat}}{I_{D0}}=(1-x{)}^2$

Both equal 1 at $x=0$ and 0 at $x=1$. The two curves agree well in between. Changing $z$ in the program shows that agreement improves as $|V_{bi}/V_P|$ decreases (the book states agreement improves with increasing $|V_P/V_{bi}|$: the $V_{bi}$ corrections become small and the exact expression approaches the square law).

MATLAB program:

% Exercise 15.2 -- Comparison of IDsat Relationships
% Computational parameters
clear
z=-0.4;                 % z = Vbi/VP
x=linspace(0,1);        % x = VG/VP
% Eq. (15.13) ("P-theory"); y = IDsat/ID0
Num=(x-1)-(2/3)*(z-1)*(1-((z-x)./(z-1)).^(1.5));
Den=-1-(2/3)*(z-1)*(1-(z/(z-1))^(1.5));
yP=Num./Den;
% Square-law theory
yS=(1-x).^2;
% Plotting result
close
plot(x,yP,x,yS,'--');grid
xlabel('VG/VP');ylabel('IDsat/ID0');
text(0.38,0.4,'Square-Law')
text(0.27,0.3,'Eq.(15.13)')
text(0.8,0.83,'Vbi/VP=-0.4')

Logic: x sweeps $V_G/V_P$ from 0 to 1; the numerator and denominator are evaluated from the normalized formula above (element-wise ./ and .^ because x is a vector); plot overlays the solid exact curve and dashed square-law curve (Fig. above, both falling monotonically from 1 to 0 with the square law slightly different in the middle).

Exercise 15.3: Series source and drain resistance

Problem. Show that $R_S$ and $R_D$ (Fig. 15.18) are accounted for by replacing $V_D\to V_D-I_D(R_S+R_D)$ and $V_G\to V_G-I_D{R}_S$ in Eqs. (15.9), (15.12), (15.13).

Solution. Voltage drops at the channel ends change the channel limits:

$V(0)=I_D{R}_S,V(L)=V_D-I_D{R}_D$

Putting these limits into (15.4), (15.5):

I_D=\frac{2qZ\mu_nN_Da}{L}\int_{I_DR_S}^{V_D-I_DR_D}\left[1-\frac{W(V)}{a}\right]dV \tag{15.5'}

$W(V)/a$ from (15.8) is unchanged since the gate is still at $V_G$ and the junction still sees $V_{bi}+V-V_G$. Evaluating the integral with the new limits:

I_D=G_0\left\{[V_D-I_DR_D-I_DR_S]-\frac{2}{3}\frac{(V_D-I_DR_D+V_{bi}-V_G)^{3/2}-(I_DR_S+V_{bi}-V_G)^{3/2}}{(V_{bi}-V_P)^{1/2}}\right\} \tag{15.9'}

Now check the replacement rule. With $V_D^{\prime }=V_D-I_D(R_S+R_D)$ and $V_G^{\prime }=V_G-I_D{R}_S$:

$V_D^{\prime }+V_{bi}-V_G^{\prime }=V_D-I_D{R}_D+V_{bi}-V_G,V_{bi}-V_G^{\prime }=I_D{R}_S+V_{bi}-V_G$

so (15.9) with primed voltages is exactly (15.9’).

Pinch-off: $W\to a$ when $V(L)=V_{Dsat}-I_{Dsat}{R}_D$. From (15.6),

a=\left[\frac{2K_S\varepsilon_0}{qN_D}(V_{bi}+V_{Dsat}-I_{Dsat}R_D-V_G)\right]^{1/2} \tag{15.11'}

and from (15.7) $a=[\dots (V_{bi}-V_P){]}^{1/2}$. Equating,

The gate-to-channel voltage at the drain end involves $V_G$ itself, so the condition is $V_{bi}+V_{Dsat}-I_{Dsat}{R}_D-V_G=V_{bi}-V_P$, i.e.

V_{Dsat}-I_{Dsat}R_D=V_G-V_P \tag{15.12'}

Hence, in terms of the intrinsic drain-end channel potential, $V_D^{\prime }$ with $V_G^{\prime }$: $V_{Dsat}^{\prime }=V_G^{\prime }-V_P$ gives $V_{Dsat}-I_{Dsat}(R_S+R_D)=V_G-I_{Dsat}{R}_S-V_P$, which is identical to (15.12’). Setting $V_D=V_{Dsat}$, $I_D=I_{Dsat}$ in (15.9) and using (15.12’):

I_{Dsat}=G_0\left\{(V_G-I_{Dsat}R_S-V_P)-\frac{2}{3}(V_{bi}-V_P)\left[1-\left(\frac{I_{Dsat}R_S+V_{bi}-V_G}{V_{bi}-V_P}\right)^{3/2}\right]\right\} \tag{15.13'}

which is (15.13) with $V_G\to V_G-I_{Dsat}{R}_S$. So the rule works.

Remarks. (i) The primed equations are implicit in $I_D$; no closed form exists, but numerical iteration solves them easily (Problem 15.7). (ii) A shortcut: change the integration variable to $V^{\prime }=V-I_D{R}_S$ and require the same form as (15.5); this works but teaches little. (iii) The saturated current is still flat in $V_D$, but at a lower value, because $R_S$ makes the gate bias seen by the channel less favorable (source degeneration, negative feedback).

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15.2.4 a.c. Response

Treat the J-FET as a two-port (Fig. 15.19a): input gate-source, output drain-source. First consider low frequencies where capacitances are negligible.

Input. The gate-source port sees a reverse-biased diode, which is (to first order) an open circuit at low frequencies.

Output. The d.c. drain current is $I_D(V_D,V_G)$. Superimposing small a.c. voltages $v_d$ and $v_g$, the drain current becomes $I_D(V_D,V_G)+i_d$, quasi-statically:

I_D(V_D,V_G)+i_d=I_D(V_D+v_d,\,V_G+v_g) \tag{15.15a}

i_d=I_D(V_D+v_d,V_G+v_g)-I_D(V_D,V_G) \tag{15.15b}

Taylor expand about the operating point, keeping first-order terms:

I_D(V_D+v_d,V_G+v_g)=I_D(V_D,V_G)+\frac{\partial I_D}{\partial V_D}\bigg|_{V_G}v_d+\frac{\partial I_D}{\partial V_G}\bigg|_{V_D}v_g \tag{15.16}

Substituting in (15.15b):

i_d=\frac{\partial I_D}{\partial V_D}\bigg|_{V_G}v_d+\frac{\partial I_D}{\partial V_G}\bigg|_{V_D}v_g \tag{15.17}

The partial derivatives are conductances. Define

g_d\equiv\frac{\partial I_D}{\partial V_D}\bigg|_{V_G=\text{const}}\quad\text{(drain or channel conductance)} \tag{15.18a}

g_m\equiv\frac{\partial I_D}{\partial V_G}\bigg|_{V_D=\text{const}}\quad\text{(transconductance or mutual conductance)} \tag{15.18b}

i_d=g_dv_d+g_mv_g \tag{15.19}

This is the a.c. KCL at the drain node: a conductance $g_d$ from drain to source in parallel with a voltage-controlled current source $g_m{v}_g$ (Fig. 15.19b, with an open circuit at the gate). The parameter $g_m$ plays a role analogous to $\alpha$ and $\beta$ in BJT analysis.

Table 15.1: J-FET small-signal parameters (by direct differentiation of (15.9) and (15.13); $G_0=2qZ{\mu }_n{N}_{D}a/L$):

	Below pinch-off ($V_D\le V_{Dsat}$)	Above pinch-off ($V_D\ge V_{Dsat}$)
$g_d$	$G_0\left[1-{\left(\frac{V_D+V_{bi}-V_G}{V_{bi}-V_P}\right)}^{1/2}\right]$	$0$
$g_m$	$G_0\frac{(V_D+V_{bi}-V_G{)}^{1/2}-(V_{bi}-V_G{)}^{1/2}}{(V_{bi}-V_P{)}^{1/2}}$	$G_0\left[1-{\left(\frac{V_{bi}-V_G}{V_{bi}-V_P}\right)}^{1/2}\right]$

Derivations: $\partial /\partial V_D$ of (15.9) gives $G_0\{1-(V_D+V_{bi}-V_G{)}^{1/2}/(V_{bi}-V_P{)}^{1/2}\}$. $\partial /\partial V_G$ of (15.9) gives $G_0\{-\frac{2}{3}\cdot (-\frac{3}{2})[(V_D+V_{bi}-V_G{)}^{1/2}-(V_{bi}-V_G{)}^{1/2}]/(V_{bi}-V_P{)}^{1/2}\}$. For saturation differentiate (15.13) with respect to $V_G$: $G_0\{1-\frac{2}{3}(V_{bi}-V_P)\cdot (-\frac{3}{2})\dots \}$; more simply, $I_{Dsat}=G_0\{V_G-V_P-\frac{2}{3}(V_{bi}-V_P)+\frac{2}{3}(V_{bi}-V_G{)}^{3/2}(V_{bi}-V_P{)}^{-1/2}\}$, whose $V_G$ derivative is $G_0\{1-(V_{bi}-V_G{)}^{1/2}(V_{bi}-V_P{)}^{-1/2}\}$. The result $g_d=0$ in saturation matches the zero slope of the characteristic.

High frequency. The gate $pn$ junctions are reverse biased, so each is represented adequately by its depletion capacitance. That capacitance is split between gate-source ($C_{gs}$) and gate-drain ($C_{gd}$), giving Fig. 15.19(c): $C_{gs}$ and $C_{gd}$ added to the low-frequency circuit.

Exercise 15.4: Effective transconductance with $R_S$, $R_D$

Problem. Using the low-frequency circuit of Fig. 15.19(b) for a saturation-biased J-FET, show that $R_S$ and $R_D$ give a reduced effective transconductance $g_m^{\prime }=g_m/(1+g_m{R}_S)$.

Solution. In saturation $g_d=0$, so replace $g_d$ by an open circuit and insert $R_S$, $R_D$ at the proper nodes (Fig. E15.4). The controlling voltage is the gate-to-intrinsic source voltage $v_g-i_d{R}_S$:

$i_d=g_m(v_g-i_d{R}_S)$

$i_d(1+g_m{R}_S)=g_m{v}_g$

$i_d=\frac{g_m}{1+g_m{R}_S}{v}_g\equiv g_m^{\prime }{v}_g,g_m^{\prime }=\frac{g_m}{1+g_m{R}_S}$

$R_D$ carries the current $i_d$ without affecting the controlling voltage, so it does not change $g_m^{\prime }$ when $g_d=0$. $R_S$ reduces $g_m^{\prime }$ appreciably when $g_m{R}_S$ is comparable to or larger than 1. This is negative feedback.

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15.3 MESFET

15.3.1 General Information

A rectifying metal-semiconductor (Schottky) contact has a bias-controllable depletion region just like a $pn$ junction (Chapter 14). So one can build FETs with Schottky gates: MESFETs (metal-semiconductor FETs). Fig. 15.20 shows a simplified perspective of a GaAs MESFET (source and drain on $n^{+}$ regions, gate metal on $n$-GaAs, on a semi-insulating GaAs substrate) and an idealized cross section.

Commercial MESFETs are GaAs-based $n$-channel devices, chosen for GaAs’s superior electron transport. Metal-insulator-GaAs FETs were historically hard to make, so MESFET fabrication became the most mature GaAs technology. GaAs MESFETs are the heart of MMICs (monolithic microwave integrated circuits) and are sold as discrete devices for amplifiers and oscillators operating above 5 GHz.

Two types (Fig. 15.21).

• D-MESFET (depletion mode): a gate bias further depletes the subgate region and reduces channel conductance (like the J-FET). It is normally on at $V_G=0$.
• E-MESFET (enhancement mode): built so the built-in voltage of the metal-semiconductor contact alone totally depletes the channel. A forward gate bias is needed to shrink the depletion width and obtain current. It is normally off.

Fig. 15.21 shows implanted $n$ and $n^{+}$ regions, a Ti/Pt/Au Schottky gate contact, AuGe/Ni ohmic contacts, and a passivation insulator. Analog circuits (including MMICs) almost exclusively use D-MESFETs. Digital logic uses both D- and E-MESFETs.

High frequency demands extremely short channels: gate (active channel) length is routinely 1 $\mu$m, and discrete GaAs MESFETs in the 1993 Hewlett-Packard catalog have nominal gate length of 0.25 $\mu$m.

15.3.2 Short-Channel Considerations

The J-FET theory applies to the MESFET if all assumptions hold. For short channels two are suspect:

1. $L\gg a$ (and hence the gradual channel approximation).
2. Low field: the drift velocity is assumed $v={\mu }_0\mathcal{E}$. With $V_D=1$ V across $L=1\mu$m, the average field is $\bar{\mathcal{E}}=V_D/L=10^4$ V/cm. The field near the drain is larger. At $10^4$ V/cm the Si electron drift velocity (Fig. 3.4) departs markedly from the linear extrapolation, and in GaAs the failure sets in at an even lower field.

Three modified models follow.

Variable mobility model

Use Eq. (3.3) with $\beta =1$:

v=\frac{\mu_0\mathcal{E}}{1+\mu_0\mathcal{E}/v_{sat}} \tag{15.20}

\mu(\mathcal{E})=\frac{|v|}{|\mathcal{E}|}=\frac{\mu_0}{1+\mu_0|\mathcal{E}|/v_{sat}} \tag{15.21}

Substituting $\mu (\mathcal{E})$ for ${\mu }_n$ in (15.1) with $\mathcal{E}=-dV/dy$ and redoing the derivation gives (derived in Problem 15.12)

I_D=\frac{I_D(\text{long-channel})}{1+\dfrac{\mu_0V_D}{v_{sat}L}},\qquad 0\le V_D\le V_{Dsat} \tag{15.22}

where $I_D$(long-channel) is from (15.9) (with ${\mu }_0$). Above pinch-off, $I_D$(long)$\to I_{Dsat}$(long) and $V_D\to V_G-V_P$. For a single-gate MESFET (Fig. 15.20) replace $2a$ by $a$ in the long-channel equations. $I_D$ is always reduced relative to the long-channel case since $\mu (\mathcal{E})\le {\mu }_0$; when $v\ll v_{sat}$, ${\mu }_0{V}_D/(v_{sat}L)\ll 1$ and the long-channel result returns. This model suits moderate-length FETs ($L\gtrsim 10\mu$m) but cannot capture the failure of the gradual channel approximation.

Saturated velocity model

In long channels, current saturation is caused by pinch-off near the drain. In short channels another mechanism exists. Suppose $v=v_{sat}$ at a point $y_1<L$. The current there is

I(y_1)=qv_{sat}N_DZ[a-W(y_1)] \tag{15.23}

Current continuity requires $I(y>y_1)=I(y_1)$. Since $v$ cannot exceed $v_{sat}$ beyond $y_1$, (15.23) forces $W(y)$ to stay constant for $y_1\le y\le L$ (Fig. 15.22). This needs an appreciable field in the subgate depletion region with some field lines ending on charge outside the gated region, the opposite of the gradual channel assumption. Though the channel is only partly constricted, $I_D$ has saturated. A larger $V_D$ just moves $y_1$ toward the source. In general, saturation occurs when the channel pinches off or when $v\to v_{sat}$ at $y=L$.

For channels of a few microns or less, $W$ for $y_1\le y\le L$ differs little from $W(0)$:

I_{Dsat}=I(y_1)\approx qv_{sat}N_DZ[a-W(0)] \tag{15.24}

W(0)=\left[\frac{2K_S\varepsilon_0}{qN_D}(V_{bi}-V_G)\right]^{1/2}=a\left(\frac{V_{bi}-V_G}{V_{bi}-V_P}\right)^{1/2} \tag{15.25}

so $I_{Dsat}=q{v}_{sat}{N}_{D}Za\left[1-\sqrt{(V_{bi}-V_G)/(V_{bi}-V_P)}\right]$. This fits $L\sim 1\mu$m GaAs MESFET data fairly well. Note that $I_{Dsat}$ depends linearly on $\sqrt{V_{bi}-V_G}$, and the velocity, not mobility, sets the current: $g_m$ is nearly constant for $V_G$ well above $V_P$.

Two-region model

The saturated-velocity model gives only $I_{Dsat}$. The two-region model gives a complete characteristic:

• For $0\le y\le y_1$: gradual channel approximation and long-channel theory with $v={\mu }_0\mathcal{E}$.
• For $y_1\le y\le L$: $v=v_{sat}$.
• The transition $y_1$ is where $|\mathcal{E}|={\mathcal{E}}_{sat}=v_{sat}/{\mu }_0$.

Hence the characteristics for $V_D\le V_{Dsat}$ come from (15.9) (or the single-gate equivalent), and for $V_D>V_{Dsat}$ set $I_D=I_{Dsat}=I_D{|}_{V_D=V_{Dsat}}$. In general $V_{Dsat}\ne V_G-V_P$, and (15.13) is not used. $V_{Dsat}$ is the drain voltage at which $|\mathcal{E}|$ reaches ${\mathcal{E}}_{sat}$ at $y=L$ (see Problem 15.13). Solving the long-channel relations for $V(y)$ (Problem 15.3) and differentiating with respect to $y$ at $y=L$ yields

\mathcal{E}_{sat}L=\frac{(V_{bi}-V_P)\left[3\left(u^2-w^2\right)-2\left(u^3-w^3\right)\right]}{3\,(u-1)},\quad u=\left(\frac{V_{Dsat}+V_{bi}-V_G}{V_{bi}-V_P}\right)^{1/2},\ w=\left(\frac{V_{bi}-V_G}{V_{bi}-V_P}\right)^{1/2} \tag{15.26}

with ${\mathcal{E}}_{sat}<0$ in the book’s sign convention. This is solved numerically for $V_{Dsat}$ (the derivation is Problem 15.13).

Fig. 15.23: normalized two-region characteristics for $V_{bi}=1$ V, $V_P=-2.5$ V, ${\mathcal{E}}_{sat}=-5\times 10^3$ V/cm, $L=1\mu$m, normalized to the $V_G=0$ saturation current $I_{D0}$ of an equivalent long-channel FET. Compared to Fig. 15.16: $V_{Dsat}$ is much lower and $I_{Dsat}/I_{D0}$ is reduced. $I_{Dsat}$ varies with $V_G$ roughly as (15.24). There is a slope discontinuity at $V_D=V_{Dsat}$, so the curves look crude, but they give a reasonable first-order match to observed short-channel curves. Accurate short-channel modeling needs a numerical two-dimensional solution of the electrostatic and current equations.

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15.4 Summary

The modulation of the conductivity of a semiconductor by an electric field normal to its surface is the field effect. The chapter began with the history of the field-effect family. The rest was devoted to the J-FET and MESFET. J-FET operation was developed qualitatively (linear region, slope-over, pinch-off, saturation, gate pinch-off) and quantitatively (classic long-channel $I_D$-$V_D$ derivation using the gradual channel approximation). The channel conductance $g_d$ and transconductance $g_m$ are the key parameters for the small-signal a.c. model. The MESFET discussion stressed short-channel physics: variable mobility, velocity saturation, and the two-region model, as modifications to the long-channel J-FET theory.

Key formulas.

$I_D=G_0\left\{V_D-\frac{2}{3}\frac{(V_D+V_{bi}-V_G{)}^{3/2}-(V_{bi}-V_G{)}^{3/2}}{(V_{bi}-V_P{)}^{1/2}}\right\},V_{Dsat}=V_G-V_P,G_0=\frac{2qZ{\mu }_n{N}_{D}a}{L}$

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Problems

Problem 15.1: Quick quiz

The OCR lost the wording of parts (b), (d), (e), (g). I reconstruct them from the chapter content and state the reconstruction each time.

(a) Define “field effect.” The modulation of the conductivity of a semiconductor by an electric field applied normal to its surface.

(b) (Reconstructed) How do the source, drain and gate get their names? Why was the J-FET called unipolar? Source: carriers enter the semiconductor from the external circuit. Drain: carriers leave. Gate: controlling or gating action. Unipolar: only one carrier type (electrons in an $n$-channel device) carries the current.

(c) For a $p$-channel J-FET ($n^{+}$-$p$ gates, $p$ region between source and drain), does $I_D$ flow into or out of the drain under normal operation? Holes are the carriers; they move from source to drain, so positive current flows out of the drain contact into the external circuit. (Opposite of the $n$-channel case, where conventional current flows into the drain.) Normal biasing is $V_G\ge 0$ and $V_D\le 0$ so the $n^{+}p$ gate junctions stay reverse biased.

(d) (Reconstructed) Why does $I_D$ saturate for $V_D>V_{Dsat}$, and why is $I_D\ne 0$ at pinch-off? The voltage in excess of $V_{Dsat}$ is dropped across a short depleted section $\Delta L$; the source-to-pinch-off region keeps the same shape and same end-point voltages, so the same current flows. $I_D$ cannot be zero at pinch-off, because zero current would give zero voltage drop along the channel, which would remove the pinch-off.

(e) What is meant by “pinch-off”? Complete depletion of the channel (top and bottom depletion regions touching) at some point. In the drain-end sense it occurs at $V_D=V_{Dsat}=V_G-V_P$. In the gate sense, $V_G=V_P$ pinches off the whole channel at $V_D=0$.

(f) Mathematical definition of drain conductance and transconductance.

$g_d={\frac{\partial I_D}{\partial V_D}|}_{V_G},g_m={\frac{\partial I_D}{\partial V_G}|}_{V_D}$

(g) (Reconstructed) Sketch the low-frequency small-signal equivalent circuit of a J-FET in saturation. Open circuit between $G$ and $S$ (reverse-biased gate). Between $D$ and $S$: a current source $g_m{v}_g$ in parallel with $g_d$, with $g_d\approx 0$ in saturation (from the flat characteristics of Fig. 15.16), so only the current source $g_m{v}_{gs}$ remains. Adding $C_{gs}$ and $C_{gd}$ gives the high-frequency model.

(h) What do MESFET, D-MESFET, E-MESFET stand for? Metal-semiconductor field-effect transistor; depletion-mode MESFET (normally on); enhancement-mode MESFET (normally off).

(i) Why is the magnitude of the electric field in the channel of concern in modeling short-channel MESFETs? In a short channel the field $\sim V_D/L$ becomes large (e.g. $10^4$ V/cm), so the drift velocity is no longer ${\mu }_0\mathcal{E}$: it saturates, which changes current saturation and invalidates the long-channel theory.

(j) Primary difference between the long-channel and two-region short-channel $I_D$-$V_D$ theories? Long-channel: saturation occurs only by pinch-off ($V_{Dsat}=V_G-V_P$) with $v={\mu }_0\mathcal{E}$ everywhere. Two-region: the channel is split into a low-field region ($v={\mu }_0\mathcal{E}$) and a velocity-saturated region ($v=v_{sat}$); saturation occurs when $\mathcal{E}$ at the drain end reaches ${\mathcal{E}}_{sat}$, at a lower $V_{Dsat}$ and lower $I_{Dsat}$.

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Problem 15.2: The composite transistor (Fig. P15.2)

An $n$-type bar has ohmic contacts D (top) and B (bottom), and $p^{+}$-$n$ step junctions on its two sides with contacts E and C. $d$ is the separation of the two $p^{+}$ regions and $L$ their lateral length. (OCR damaged some conditions; I use the plausible original: $d\ll L_p$ in (a),(b); I assume (a) asks for $I_C$ versus $V_{CB}$.)

(a) D-B tied, $d\ll L_p$, $V_{EB}>0$, $V_{CB}<0$. Sketch $I_C$ (out of C) versus the collector-base voltage at several constant $I_E$.

Reasoning. E-$n$-C is a $p^{+}nn$… a lateral $p^{+}$-$n$-$p^{+}$ BJT with E as emitter (forward biased, $V_{EB}>0$), the $n$ bar (D-B) as base, and C as collector (reverse biased). Since $d\ll L_p$, holes injected from E cross the narrow base without recombining, so the transport factor is about 1, and the injection efficiency is about 1 ($p^{+}$ emitter). Hence $\alpha \approx 1$:

$I_C\approx \alpha I_E\approx I_E$

Sketch: common-base output characteristics, flat horizontal lines, spaced by the chosen $I_E$ values, nearly independent of $V_{CB}$ in reverse bias, with a slight upward tilt (base-width modulation). As $V_{CB}$ moves toward zero and becomes positive (collector junction forward biased, about 0.4 to 0.5 V), the collector starts injecting holes back and $I_C$ drops through zero and goes negative. At large reverse $V_{CB}$ the curves rise abruptly (avalanche breakdown, multiplication).

(b) E-C tied, D-B tied, $d\ll L_p$. Sketch the current into the E-C leads versus the voltage from E-C to D-B.

Reasoning. The two $p^{+}$-$n$ junctions are in parallel, with the same voltage. The structure is simply a diode of about twice the single-junction area. Forward bias ($V>0$): exponential $I\approx I_0(e^{qV/kT}-1)$ (current rising sharply near 0.6 V for Si). Reverse bias: small, nearly constant saturation current $-I_0$ (with slight generation increase), then abrupt breakdown at $V=-V_{BR}$. The two junctions at the same potential inject equally into the region between them, so there is no hole current across the gap $d$ and no transistor action.

(c) E-C tied, $d<2W_{BR}$, $L\approx$ the bar length between D and B, $V_{DB}>0$, $V_{EB}<0$. Sketch $I_D$ versus $V_{DB}$ at several $V_{EB}$.

Reasoning. Now the $p^{+}$ regions are reverse-biased gates. B acts as source, D as drain, the gap $d$ is the channel ($2a=d$): this is a J-FET. The condition $d<2W_{BR}$ guarantees pinch-off ($W\to a=d/2$) occurs before junction breakdown. The sketch is the J-FET family: for each gate bias a linear rise, slope-over, and saturation at $V_{DBsat}=V_{EB}-V_P$ with $I_{Dsat}$ falling as $V_{EB}$ becomes more negative; for $V_{EB}\le V_P$, $I_D=0$. At large $V_{DB}$ all curves rise abruptly (breakdown near the drain end).

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Problem 15.3: Voltage along the channel

Problem. (a) Derive an expression for the position $y/L$ where a given channel voltage $V(y)$ occurs. (b) For $V_G=0$, $V_D=5$ V, $V_{bi}=1$ V, $V_P=-8$ V, find $y/L$ for $V(y)=1,2,3,4$ V and compare with Fig. 15.11(c).

(a) Solution. Following the hint, put $L\to y$, $V_D\to V(y)$ in (15.4):

$I_{D}y=2qZ{\mu }_n{N}_D{\int }_0^{V(y)}[a-W(V)]dV$

Divide by (15.4) itself:

$\frac{y}{L}=\frac{{\int }_0^{V(y)}[1-W/a]dV}{{\int }_0^{V_D}[1-W/a]dV}$

Evaluate the integrals as in (15.9) with $F(V)\equiv V-\frac{2}{3}\left[(V+V_{bi}-V_G{)}^{3/2}-(V_{bi}-V_G{)}^{3/2}\right]/(V_{bi}-V_P{)}^{1/2}$:

$\boxed{\frac{y}{L}=\frac{F(V(y))}{F(V_D)}=\frac{V(y)-\frac{2}{3}\frac{[V(y)+V_{bi}-V_G{]}^{3/2}-(V_{bi}-V_G{)}^{3/2}}{(V_{bi}-V_P{)}^{1/2}}}{V_D-\frac{2}{3}\frac{[V_D+V_{bi}-V_G{]}^{3/2}-(V_{bi}-V_G{)}^{3/2}}{(V_{bi}-V_P{)}^{1/2}}}}$

(b) Numbers. $V_{bi}-V_P=9$ V so $(V_{bi}-V_P{)}^{1/2}=3$, and with $V_G=0$:

$F(V)=V-\frac{2}{9}\left[(V+1{)}^{3/2}-1\right]$

(Check that we are below pinch-off: $V_{Dsat}=V_G-V_P=8$ V $>5$ V.)

$F(5)=5-\frac{2}{9}(6^{3/2}-1)=5-\frac{2}{9}(13.697)=5-3.044=1.956$

$V(y)$ (V)	$F(V)$	$y/L$
1	$1-\frac{2}{9}(2.828-1)=0.594$	0.304
2	$2-\frac{2}{9}(5.196-1)=1.068$	0.546
3	$3-\frac{2}{9}(8-1)=1.444$	0.738
4	$4-\frac{2}{9}(11.180-1)=1.738$	0.888

Comparison. Fig. 15.11(c) draws 1, 2, 3, 4 V at equal spacing, i.e. $y/L=0.2,0.4,0.6,0.8$. The true positions are $0.30,0.55,0.74,0.89$. The voltage rises slowly near the source and steeply near the drain (the last volt occurs in the last 11% of the channel). Reason: the channel is narrowest near the drain, so the resistance per unit length is largest there, and for the same current the voltage drop per unit length is largest there.

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Problem 15.4: $V_{Dsat}$ from the maximum of $I_D$

Problem. If (15.9) is evaluated for $V_D>V_{Dsat}$, $I_D$ is a peaked function of $V_D$ with its maximum at $V_{Dsat}$. Use the maximum condition to derive (15.12) directly from (15.9).

Solution. Set $d{I}_D/d{V}_D=0$:

$\frac{d{I}_D}{d{V}_D}=G_0\left\{1-\frac{(V_D+V_{bi}-V_G{)}^{1/2}}{(V_{bi}-V_P{)}^{1/2}}\right\}=0$

$(V_D+V_{bi}-V_G{)}^{1/2}=(V_{bi}-V_P{)}^{1/2}$

$V_D+V_{bi}-V_G=V_{bi}-V_P$

$\boxed{V_{Dsat}=V_G-V_P}$

It is a maximum since $d^2{I}_D/d{V}_D^2=-\frac{G_0}{2}\frac{1}{(V_D+V_{bi}-V_G{)}^{1/2}(V_{bi}-V_P{)}^{1/2}}<0$.

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Problem 15.5: J-FET with the bottom gate grounded (Fig. P15.5)

Long-channel J-FET, bottom gate tied to the source and grounded ($V_{GB}=0$), top gate at $V_G\equiv V_{GT}\le 0$, $V_D\ge 0$. Let $A=2K_S{\epsilon }_0/(q{N}_D)$, so $W=\sqrt{A(V_{bi}-V_A)}$ and $a=\sqrt{A(V_{bi}-V_P)}$ where $V_P$ is the pinch-off voltage with the two gates tied.

(a) Sketch the depletion regions when $V_{GT}$ pinches off the channel at $V_D=0$. The bottom junction is at equilibrium: a thin depletion layer of width $W_B(0)=\sqrt{A{V}_{bi}}$ at the bottom. The top depletion layer is much wider and must extend down to touch it, so $W_T=2a-W_B(0)$: a deep depletion region from the top, a thin one from the bottom, meeting at a plane closer to the bottom than the midplane $x=a$.

(b) $V_P=-8$ V (gates tied), $V_{bi}=1$ V. Find the top-gate pinch-off voltage $V_{PT}$ with $V_{GB}=0$, $V_D=0$.

$a=\sqrt{A\cdot 9}=3\sqrt{A}(\text{since }{V}_{bi}-V_P=9\text{ V}),W_B(0)=\sqrt{A\cdot 1}=\sqrt{A}$

Pinch-off condition:

$W_T=2a-W_B(0)=6\sqrt{A}-\sqrt{A}=5\sqrt{A}$

$\sqrt{A(V_{bi}-V_{PT})}=5\sqrt{A}$

$V_{bi}-V_{PT}=25$

$\boxed{V_{PT}=1-25=-24\text{V}}$

Consistent with (a): the top depletion layer must span 5/6 of the thickness $2a$ (more than $a$), requiring much more reverse bias than the symmetric $-8$ V where each layer spans only $a$ (depletion $\propto \sqrt{V}$, so $25/9$ more voltage-equivalent). Assumes no breakdown at $-24$ V.

(c) $V_{PT}<V_{GT}<0$, drain raised to pinch-off. Sketch. Both junctions get more reverse biased toward the drain. The top is always more reverse biased ($V-V_{GT}$) than the bottom ($V-0$), so the top layer is thicker at every $y$. The wedges meet only at the drain end, at a point shifted toward the bottom gate.

(d) Expression for $V_{Dsat}$ using only voltages. Pinch-off at $y=L$ where $V=V_{Dsat}$: $W_T+W_B=2a$:

$\sqrt{A(V_{bi}+V_{Dsat}-V_{GT})}+\sqrt{A(V_{bi}+V_{Dsat}-0)}=2\sqrt{A(V_{bi}-V_P)}$

$\boxed{\sqrt{V_{bi}+V_{Dsat}-V_{GT}}+\sqrt{V_{bi}+V_{Dsat}}=2\sqrt{V_{bi}-V_P}}$

(e) Larger or smaller than the tied-gate value $V_{Dsat}=V_{GT}-V_P$? Let $u=V_{bi}+V_{Dsat}$ and let $u^{\prime }$ be the tied-gate value, $u^{\prime }=V_{bi}-V_P+V_{GT}$. The left side of (d), $f(u)=\sqrt{u-V_{GT}}+\sqrt{u}$, increases with $u$. At $u^{\prime }$: $f(u^{\prime })=\sqrt{V_{bi}-V_P}+\sqrt{u^{\prime }}$. Because $V_{GT}<0$, $u^{\prime }<V_{bi}-V_P$, so $f(u^{\prime })<2\sqrt{V_{bi}-V_P}$. Hence the true root satisfies $u>u^{\prime }$:

$V_{Dsat}(V_{GB}=0)>V_{Dsat}(V_{GB}=V_{GT})$

Physically, the bottom junction is less reverse biased, its depletion layer is thinner, and a larger drain voltage is needed to close the channel.

(f) $I_D(V_D,V_{GT})$. Channel thickness $2a-W_T-W_B$:

$I_{D}L=qZ{\mu }_n{N}_D{\int }_0^{V_D}\left[2a-W_T(V)-W_B(V)\right]dV$

with $W_T=\sqrt{A(V_{bi}+V-V_{GT})}$, $W_B=\sqrt{A(V_{bi}+V)}$. Integrating,

$I_D=\frac{qZ{\mu }_n{N}_D}{L}\left\{2a{V}_D-\frac{2}{3}\sqrt{A}[(V_D+V_{bi}-V_{GT}{)}^{3/2}-(V_{bi}-V_{GT}{)}^{3/2}+(V_D+V_{bi}{)}^{3/2}-V_{bi}^{3/2}]\right\}$

Using $\sqrt{A}=a/\sqrt{V_{bi}-V_P}$ and $G_0=2qZ{\mu }_n{N}_{D}a/L$:

$\boxed{I_D=G_0\left\{V_D-\frac{1}{3}\frac{(V_D+V_{bi}-V_{GT}{)}^{3/2}-(V_{bi}-V_{GT}{)}^{3/2}+(V_D+V_{bi}{)}^{3/2}-V_{bi}^{3/2}}{(V_{bi}-V_P{)}^{1/2}}\right\}}$

valid for $V_D\le V_{Dsat}$ of part (d). Check: if both gates were at $V_{GT}$ the bracket doubles and $\frac{1}{3}\to \frac{2}{3}$, recovering (15.9).

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Problem 15.6: Linearly graded channel (Fig. P15.6)

The net donor doping rises linearly from the $p^{+}$-$n$ junction at $x=0$ (zero) to a maximum at the center $x=a$ and falls symmetrically to zero at $x=2a$ (assumed reading of the figure). Let $N_D-N_A=\kappa x$ for $0\le x\le a$ and $\kappa (2a-x)$ for $a\le x\le 2a$, $\kappa$ = grade constant (cm${}^{-4}$).

(a) Depletion width. One side is $p^{+}$, so depletion lies in the $n$ side. Poisson on $0\le x\le W$ (junction at $x=0$):

$\frac{d\mathcal{E}}{dx}=\frac{q\kappa x}{K_S{\epsilon }_0}\Rightarrow \mathcal{E}(x)=-\frac{q\kappa }{2K_S{\epsilon }_0}(W^2-x^2)(\mathcal{E}(W)=0)$

Voltage across the junction:

$V_{bi}-V_A={\int }_0^W|\mathcal{E}|dx=\frac{q\kappa }{2K_S{\epsilon }_0}\left(W^3-\frac{W^3}{3}\right)=\frac{q\kappa W^3}{3K_S{\epsilon }_0}$

$\boxed{W={\left[\frac{3K_S{\epsilon }_0}{q\kappa }(V_{bi}-V_A)\right]}^{1/3}}$

(The symmetric linearly graded junction of Section 5.2.5 has 12 instead of 3; here only one side of the junction is graded.)

(b) $I_D$-$V_D$. With gates tied, $V_A=V_G-V(y)$, so $W/a=[(V_{bi}+V-V_G)/(V_{bi}-V_P){]}^{1/3}$, where $a^3=\frac{3K_S{\epsilon }_0}{q\kappa }(V_{bi}-V_P)$ defines $V_P$. The caution: the carrier density is not constant. The conducting cross-section carries

${\int }_W^{2a-W}N(x)dx=2{\int }_W^a\kappa xdx=\kappa (a^2-W^2)$

(ignore the ${\mu }_n$ doping dependence). Then

$I_D=qZ{\mu }_n\frac{dV}{dy}\kappa (a^2-W^2)\Rightarrow I_{D}L=qZ{\mu }_n\kappa a^2{\int }_0^{V_D}\left[1-{\left(\frac{W}{a}\right)}^2\right]dV$

${\left(\frac{W}{a}\right)}^2={\left(\frac{V_{bi}-V_G+V}{V_{bi}-V_P}\right)}^{2/3}$

${\int }_0^{V_D}\left[1-{\left(\frac{V_{bi}-V_G+V}{V_{bi}-V_P}\right)}^{2/3}\right]dV=V_D-\frac{3}{5}\frac{(V_D+V_{bi}-V_G{)}^{5/3}-(V_{bi}-V_G{)}^{5/3}}{(V_{bi}-V_P{)}^{2/3}}$

$\boxed{I_D=G_0^{\prime }\left\{V_D-\frac{3}{5}\frac{(V_D+V_{bi}-V_G{)}^{5/3}-(V_{bi}-V_G{)}^{5/3}}{(V_{bi}-V_P{)}^{2/3}}\right\},G_0^{\prime }=\frac{qZ{\mu }_n\kappa a^2}{L}}$

$G_0^{\prime }$ is the no-depletion conductance. $V_{Dsat}=V_G-V_P$ still holds because pinch-off is still $W=a$.

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Problem 15.7: Effect of $R_S$ and $R_D$ (MATLAB)

Task. Plot normalized $I_D/I_{D0}$ vs. $V_D$ for several $V_G$, with $G_0{R}_S=G_0{R}_D=0,0.1,0.5$, $V_{bi}=1$ V, $V_P=-2.5$ V, with $I_{D0}=I_{Dsat}{|}_{V_G=0}$ from (15.13) (the intrinsic device).

Method. Let $F(V_1,V_2;V_G)={\int }_{V_1}^{V_2}[1-W/a]dV=(V_2-V_1)-\frac{2}{3}\left[(V_2+V_{bi}-V_G{)}^{3/2}-(V_1+V_{bi}-V_G{)}^{3/2}\right]/\sqrt{V_{bi}-V_P}$. Then $I_D=G_{0}F$ with

$V_1=I_D{R}_S,V_2=\min \{V_D-I_D{R}_D,V_G-V_P\}$

(the min enforces saturation: the drain-end channel potential cannot exceed $V_G-V_P$). Let $j=I_D/I_{D0}$ and $f_0=I_{D0}/G_0$ (volts). Then $I_D{R}_S=j{f}_0(G_0{R}_S)$, so only $G_0{R}_S$, $G_0{R}_D$ appear. The equation to solve per bias point:

$h(j)=j{f}_0-F(j{f}_0{g}_{rs},\min \{V_D-j{f}_0{g}_{rd},V_G-V_P\};V_G)=0$

with $g_{rs}=G_0{R}_S$, $g_{rd}=G_0{R}_D$. $h$ is strictly increasing in $j$ (increasing $j$ raises $V_1$ and lowers $V_2$, both reducing $F$), $h(0)\le 0$, $h(1)\ge 0$. So bisection on $[0,1]$ always finds a unique root.

% Problem 15.7 -- J-FET ID-VD with series resistances Rs, Rd
clear; close all
Vbi=1; Vp=-2.5; c=Vbi-Vp;
VGlist=[0 -0.5 -1 -1.5 -2];
VD=linspace(0,5,101);
grs=[0 0.1 0.5];                      % G0*Rs = G0*Rd values
% F(V1,V2;VG): integral of (1-W/a) dV
F=@(V1,V2,VG) (V2-V1)-(2/3)*((V2+Vbi-VG).^1.5-(V1+Vbi-VG).^1.5)/sqrt(c);
f0=F(0,-Vp,0);                        % ID0/G0 (intrinsic, VG=0)
for k=1:length(grs)
  g=grs(k);                           % G0*Rs=G0*Rd=g
  figure(k); hold on
  for m=1:length(VGlist)
    VG=VGlist(m); j=zeros(size(VD));
    for n=1:length(VD)
      lo=0; hi=1;
      for it=1:60                     % bisection on j=ID/ID0
        mid=(lo+hi)/2;
        V1=mid*f0*g;
        V2=min(VD(n)-mid*f0*g, VG-Vp);
        h=mid*f0-F(V1,V2,VG);
        if h>0, hi=mid; else lo=mid; end
      end
      j(n)=(lo+hi)/2;
    end
    plot(VD,j)
  end
  grid on; xlabel('V_D (volts)'); ylabel('I_D/I_{D0}')
  title(['G_0R_S=G_0R_D=' num2str(g)])
end

Results (from running the same algorithm; $V_D=5$ V; columns $V_G=0,-0.5,-1,-1.5,-2$ V):

$G_{0}R$	$I_D/I_{D0}$ at $V_D=5$ V
0	1.000, 0.614, 0.334, 0.144, 0.035
0.1	0.956, 0.594, 0.326, 0.142, 0.035
0.5	0.820, 0.527, 0.298, 0.134, 0.034

For $V_G=0$: $I_D/I_{D0}$ at $V_D=0.5,1,2,5$ is 0.386, 0.666, 0.965, 1.000 ($G_{0}R=0$), 0.357, 0.622, 0.916, 0.956 (0.1) and 0.275, 0.493, 0.763, 0.820 (0.5).

Comment. $G_{0}R=0$ reproduces Fig. 15.16. With resistance: (i) the linear-region slope drops (resistances add in series with the channel); (ii) $I_{Dsat}$ is lower, most for $V_G=0$ (high current) and negligibly for near-pinch-off curves (low current, little $IR$ drop); (iii) the knee moves to higher terminal $V_D$ (from (15.12’), $V_{Dsat}=V_G-V_P+I_{Dsat}{R}_D$), the saturated curves remain flat, and they bunch together because $R_S$ reduces the effective gate swing (reduced $g_m$, consistent with Exercise 15.4).

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Problem 15.8: The pinch resistor

A pinch resistor is a J-FET with its gate(s) shorted to the source, a two-terminal nonlinear resistor with $V_G=0$ and applied voltage $V=V_D$.

(a) Conductances. Below pinch-off ($0\le V\le V_{Dsat}=-V_P$), from (15.9) with $V_G=0$:

$I=G_0\left\{V-\frac{2}{3}\frac{(V+V_{bi}{)}^{3/2}-V_{bi}^{3/2}}{(V_{bi}-V_P{)}^{1/2}}\right\}$

d.c. conductance:

$\boxed{G=\frac{I}{V}=G_0\left\{1-\frac{2}{3}\frac{(V+V_{bi}{)}^{3/2}-V_{bi}^{3/2}}{V(V_{bi}-V_P{)}^{1/2}}\right\}}$

a.c. conductance (this is $g_d$ at $V_G=0$):

$\boxed{g=\frac{dI}{dV}=G_0\left[1-{\left(\frac{V+V_{bi}}{V_{bi}-V_P}\right)}^{1/2}\right]}$

For $V>-V_P$: $I=I_{D0}$ is constant, so $G=I_{D0}/V$ and $g=0$.

(b) Numbers at $V=V_{Dsat}/2$. $V_P=-2$ V so $V_{Dsat}=2$ V and $V=1$ V. $Z/L=1$, $a=0.5\mu$m, $N_D=10^{16}$ cm${}^{-3}$, $V_{bi}=1$ V. Assumption: electron mobility is not given; I take ${\mu }_n\approx 1250$ cm${}^2$/V s (Si at $10^{16}$ cm${}^{-3}$, about 300 K). Also, the given $a$ and $N_D$ imply $V_{bi}-V_P=1.9$ V, not 3 V; I use the stated $V_P=-2$ V for the voltage dependence.

$G_0=2q\frac{Z}{L}{\mu }_n{N}_{D}a=2(1.6\times 10^{-19})(1)(1250)(10^{16})(0.5\times 10^{-4})=2.0\times 10^{-4}\text{S}$

With $V_{bi}-V_P=3$ V:

$\frac{I}{G_0}=1-\frac{2}{3}\frac{2^{3/2}-1}{\sqrt{3}}=1-\frac{2}{3}(1.0556)\Rightarrow \frac{I}{G_0}=0.2963\text{V}(\text{since }V=1\text{ V})$

$I=(2.0\times 10^{-4})(0.2963)=5.93\times 10^{-5}\text{A}$

$G=\frac{I}{V}=5.93\times 10^{-5}\text{S}\Rightarrow R=\frac{1}{G}\approx 16.9\text{k}\Omega$

$g=2.0\times 10^{-4}\left[1-\sqrt{\frac{2}{3}}\right]=2.0\times 10^{-4}(0.1835)=3.67\times 10^{-5}\text{S}\Rightarrow r=\frac{1}{g}\approx 27.2\text{k}\Omega$

$\boxed{R\approx 16.9\text{k}\Omega ,r\approx 27.2\text{k}\Omega }$

(Dynamic resistance exceeds static: the I-V curve bends over.)

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Problem 15.9: Cutoff frequency

$f_{max}=\frac{g_m}{2\pi C_G}$

(a) Derivation. Treat the gate input as the capacitor $C_G$ (the open circuit is replaced by the junction capacitance). An a.c. gate voltage $v_g$ draws input current $i_g=j\omega C_G{v}_g$ with magnitude $\omega C_G|v_g|$. The output (saturation, $g_d=0$) delivers $i_d=g_m{v}_g$. The current gain $|i_d/i_g|=g_m/(\omega C_G)$ falls to unity at the maximum useful frequency:

${\omega }_{max}{C}_G=g_m\Rightarrow f_{max}=\frac{g_m}{2\pi C_G}$

(analogous to the MOSFET cutoff analysis of Section 17.3.2).

(b) J-FET expression. The largest $g_m$ is the no-depletion limit $G_0=2qZ{\mu }_n{N}_{D}a/L$ (Table 15.1: saturation $g_m\to G_0$ as $V_G\to V_{bi}$). Estimate $C_G$ with both gates in parallel at pinch-off width $a$: $C_G=2\frac{K_S{\epsilon }_{0}ZL}{a}$.

$f_{max}=\frac{G_0}{2\pi C_G}=\frac{2qZ{\mu }_n{N}_{D}a/L}{2\pi \cdot 2K_S{\epsilon }_{0}ZL/a}$

$\boxed{f_{max}=\frac{q{\mu }_n{N}_D{a}^2}{2\pi K_S{\epsilon }_0{L}^2}}$

Short channels ($f\propto 1/L^2$), high mobility and heavy channel doping give higher speed.

(c) Numbers. Si, $N_D=10^{16}$, $a=0.5\mu$m, $L=5\mu$m, assuming ${\mu }_n=1250$ cm${}^2$/V s:

$f_{max}=\frac{(1.6\times 10^{-19})(1250)(10^{16})(0.5\times 10^{-4}{)}^2}{2\pi (11.8)(8.85\times 10^{-14})(5\times 10^{-4}{)}^2}=\frac{5.0\times 10^{-9}}{1.64\times 10^{-18}}\approx 3.0\times 10^9\text{Hz}$

$\boxed{f_{max}\approx 3\text{GHz}}$

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Problem 15.10: Temperature dependence of $g_m$

Setup. Saturation, $V_G=0$: $g_m=G_0\left[1-\sqrt{V_{bi}/(V_{bi}-V_P)}\right]$. Neglecting dimensional changes, $V_{bi}-V_P=q{N}_D{a}^2/(2K_S{\epsilon }_0)$ is temperature independent:

$V_{bi}-V_P=\frac{(1.6\times 10^{-19})(10^{16})(0.6\times 10^{-4}{)}^2}{2(11.8)(8.85\times 10^{-14})}=2.76\text{V}$

$G_0\propto {\mu }_n(T)$, and $V_{bi}(T)=\frac{kT}{q}\ln \frac{N_A{N}_D}{n_i^2(T)}$ with $N_A=5\times 10^{18}$, $N_D=10^{16}$:

$\frac{g_m(T)}{g_m(300)}=\frac{{\mu }_n(T)}{{\mu }_n(300)}\cdot \frac{1-\sqrt{V_{bi}(T)/2.76}}{1-\sqrt{V_{bi}(300)/2.76}}$

Model used (stated assumptions).

• $n_i(T)=10^{10}(T/300{)}^{3/2}\exp \left[-\left(\frac{E_G(T)}{2kT}-\frac{E_G(300)}{2k\cdot 300}\right)\right]$, $E_G=1.17-4.73\times 10^{-4}{T}^2/(T+636)$.
• ${\mu }_n$: Matthiessen with lattice $1430(T/300{)}^{-2.42}$ and ionized-impurity $9900(T/300{)}^{3/2}$ cm${}^2$/V s (${\mu }_n(300)\approx 1250$).

(a) Results.

$T$ (K)	$V_{bi}$ (V)	${\mu }_n(T)/{\mu }_n(300)$	$g_m(T)/g_m(300)$
225	0.972	1.588	1.477
250	0.940	1.374	1.309
275	0.908	1.174	1.146
300	0.875	1.000	1.000
325	0.841	0.853	0.874
350	0.806	0.730	0.768
375	0.771	0.629	0.679
400	0.734	0.545	0.604
425	0.698	0.475	0.541
450	0.660	0.417	0.487
475	0.622	0.368	0.442

% Problem 15.10 -- gm(T)/gm(300) for saturation-biased n-channel Si J-FET
clear; close all
k=8.617e-5; q=1.6e-19; eps=11.8*8.85e-14;
ND=1e16; NA=5e18; a=0.6e-4;
c=q*ND*a^2/(2*eps);                       % Vbi-Vp (T independent)
Eg=@(T) 1.17-4.73e-4*T.^2./(T+636);
ni=@(T) 1e10*(T/300).^1.5.*exp(-(Eg(T)./(2*k*T)-Eg(300)/(2*k*300)));
mu=@(T) 1./(1./(1430*(T/300).^-2.42)+1./(9900*(T/300).^1.5));
Vbi=@(T) k*T.*log(NA*ND./ni(T).^2);
gm=@(T) mu(T).*(1-sqrt(Vbi(T)/c));
T=225:50:475; T=[225 250 275 300 325 350 375 400 425 450 475];
loglog(T,gm(T)/gm(300),'o-',T,mu(T)/mu(300),'s--'); grid
xlabel('T (K)'); ylabel('normalized'); legend('g_m','\mu_n')
p=polyfit(log(T/300),log(gm(T)/gm(300)),1); n=-p(1)

(b) Exponent. Fit $g_m\propto T^{-n}$ to the log-log data: $n\approx 1.65$. The mobility alone behaves as $T^{-2.0}$ over this range with this model. So $g_m$ falls more slowly than ${\mu }_n$. Reason: as $T$ rises, $V_{bi}$ falls (intrinsic carriers grow), so the zero-bias depletion shrinks and the channel opens a little, partly compensating the mobility drop. Therefore the mobility is the dominant effect, with $V_{bi}$ (and $V_P$) providing a partial offset. (Numbers depend on the assumed mobility model.)

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Problem 15.11: Back-gated MESFET, two-region model

Top MS gate (built-in $V_{biT}$, voltage $V_{GT}$) and bottom $p^{+}$-$n$ gate ($V_{biB}$, $V_{GB}$), thickness $2a$ between the junctions, channel length $L$ set by the shorter MS gate. Let $V_{PT}$ be the top-gate voltage that pinches off the channel when $V_D=0$ and $V_{GB}=0$ (reading of the garbled definition).

Solution. Below saturation the two-region model uses the long-channel theory ($v={\mu }_0\mathcal{E}$) up to $V_{Dsat}$. With $A=2K_S{\epsilon }_0/(q{N}_D)$:

$I_{D}L=qZ{\mu }_0{N}_D{\int }_0^{V_D}\left[2a-W_T-W_B\right]dV,W_T=\sqrt{A(V_{biT}+V-V_{GT})},W_B=\sqrt{A(V_{biB}+V-V_{GB})}$

Integrating:

$I_D=\frac{qZ{\mu }_0{N}_D}{L}\left\{2a{V}_D-\frac{2}{3}\sqrt{A}\left[{\Sigma }_T+{\Sigma }_B\right]\right\}$

${\Sigma }_T=(V_D+V_{biT}-V_{GT}{)}^{3/2}-(V_{biT}-V_{GT}{)}^{3/2},{\Sigma }_B=(V_D+V_{biB}-V_{GB}{)}^{3/2}-(V_{biB}-V_{GB}{)}^{3/2}$

Eliminate $\sqrt{A}$ with the pinch-off definition ($W_T+W_B=2a$ at $V=0$, $V_{GT}=V_{PT}$, $V_{GB}=0$):

$2a=\sqrt{A}\left[(V_{biT}-V_{PT}{)}^{1/2}+V_{biB}^{1/2}\right]\Rightarrow \frac{\sqrt{A}}{a}=\frac{2}{(V_{biT}-V_{PT}{)}^{1/2}+V_{biB}^{1/2}}$

With $G_0=2qZ{\mu }_0{N}_{D}a/L$, $qZ{\mu }_0{N}_D/L=G_0/(2a)$, so $\frac{G_0}{2a}\cdot \frac{2}{3}\sqrt{A}=\frac{2G_0}{3}\frac{1}{D}$ with $D\equiv (V_{biT}-V_{PT}{)}^{1/2}+V_{biB}^{1/2}$:

$\boxed{I_D=G_0\left\{V_D-\frac{2}{3}\frac{{\Sigma }_T+{\Sigma }_B}{(V_{biT}-V_{PT}{)}^{1/2}+V_{biB}^{1/2}}\right\},0\le V_D\le V_{Dsat}}$

Above $V_{Dsat}$, $I_D=I_{Dsat}=I_D{|}_{V_{Dsat}}$, where $V_{Dsat}$ is found from the field condition $|\mathcal{E}(L)|={\mathcal{E}}_{sat}$ (analogue of 15.26). Check: for a symmetric device $V_{biT}=V_{biB}$, $V_{GT}=V_{GB}$, $D=2\sqrt{V_{bi}-V_P}$ and ${\Sigma }_T={\Sigma }_B$, giving (15.9). (If the single-gate variant is wanted, the same algebra with $2a\to a$ applies.)

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Problem 15.12: Derive Eq. (15.22)

Solution. Use magnitudes with $\mathcal{E}=dV/dy>0$ along the channel. The mobility is $\mu (\mathcal{E})={\mu }_0/(1+{\mu }_0\mathcal{E}/v_{sat})$. Current through the channel:

$I_D=2qZ{N}_D\mu (\mathcal{E})\mathcal{E}[a-W]=\frac{2qZ{N}_D{\mu }_0[a-W]dV/dy}{1+({\mu }_0/v_{sat})dV/dy}$

Multiply out:

$I_D+I_D\frac{{\mu }_0}{v_{sat}}\frac{dV}{dy}=2qZ{\mu }_0{N}_D[a-W]\frac{dV}{dy}$

Multiply by $dy$:

$I_{D}dy=2qZ{\mu }_0{N}_D[a-W]dV-\frac{I_D{\mu }_0}{v_{sat}}dV$

Integrate over $0\le y\le L$ ($I_D$ constant), $0\le V\le V_D$:

$I_{D}L=2qZ{\mu }_0{N}_D{\int }_0^{V_D}[a-W]dV-\frac{I_D{\mu }_0{V}_D}{v_{sat}}$

$I_D\left(L+\frac{{\mu }_0{V}_D}{v_{sat}}\right)=2qZ{\mu }_0{N}_D{\int }_0^{V_D}[a-W]dV=I_D(\text{long})L$

$\boxed{I_D=\frac{I_D(\text{long-channel})}{1+{\mu }_0{V}_D/(v_{sat}L)}}$

(For single-gate MESFET use $a$ in place of $2a$ in the long-channel factor.)

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Problem 15.13: Derive Eq. (15.26)

Solution. From Problem 15.3(a), $I_{D}y=G_{0}LF(V(y))$ with $F(V)={\int }_0^V[1-W/a]dV$ and $I_D=G_{0}F(V_D)$. Differentiate with respect to $y$:

$I_D=G_{0}L\left[1-\frac{W(V)}{a}\right]\frac{dV}{dy}$

At the drain end for $V_D=V_{Dsat}$, the transition to the velocity-saturated region occurs when the field magnitude there equals $|{\mathcal{E}}_{sat}|$ (with $\mathcal{E}=-dV/dy$, so ${\mathcal{E}}_{sat}<0$):

${\frac{dV}{dy}|}_L=-{\mathcal{E}}_{sat}=\frac{I_D}{G_{0}L[1-W(V_{Dsat})/a]}=\frac{F(V_{Dsat})}{L[1-u]}$

where $u=W(V_{Dsat})/a={\left[(V_{Dsat}+V_{bi}-V_G)/(V_{bi}-V_P)\right]}^{1/2}$. Write with $c=V_{bi}-V_P$, $w=\sqrt{(V_{bi}-V_G)/c}$ so that $V_{Dsat}=c(u^2-w^2)$:

$F(V_{Dsat})=c(u^2-w^2)-\frac{2}{3}c(u^3-w^3)=\frac{c}{3}\left[3(u^2-w^2)-2(u^3-w^3)\right]$

${\mathcal{E}}_{sat}L=-\frac{F(V_{Dsat})}{1-u}=\frac{F(V_{Dsat})}{u-1}$

$\boxed{{\mathcal{E}}_{sat}L=\frac{(V_{bi}-V_P)\left[3(u^2-w^2)-2(u^3-w^3)\right]}{3(u-1)}}$

The same result in the unsimplified form is ${\mathcal{E}}_{sat}L=\left\{V_{Dsat}-\frac{2}{3}[(V_{Dsat}+V_{bi}-V_G{)}^{3/2}-(V_{bi}-V_G{)}^{3/2}]/\sqrt{c}\right\}/\left[\sqrt{(V_{Dsat}+V_{bi}-V_G)/c}-1\right]$, solved numerically for $V_{Dsat}$.

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Problem 15.14: MATLAB two-region model

Logic. Only ${\mathcal{E}}_{sat}L$ matters. For each $V_G$:

1. $V_{Dsat}$ is the root of $\Phi (V_D)=F(V_D)/(1-u(V_D))-|{\mathcal{E}}_{sat}|L=0$ on $(0,V_G-V_P)$. $\Phi$ rises monotonically from $-|{\mathcal{E}}_{sat}|L<0$ to $+\infty$ as $u\to 1$, so there is exactly one root (found with fzero/bisection).
2. For $V_D\le V_{Dsat}$: $I_D/I_{D0}=F(V_D)/f_0$. For $V_D>V_{Dsat}$: $I_{Dsat}/I_{D0}=F(V_{Dsat})/f_0$.
3. $f_0=F(V_G=0,V_D=-V_P)=-V_P-\frac{2}{3}(V_{bi}-V_P)\left[1-{\left(\frac{V_{bi}}{V_{bi}-V_P}\right)}^{3/2}\right]$. Normalizing by $f_0$ cancels the single/double-gate factor and $G_0$.

% Problem 15.14 -- two-region model ID-VD characteristics
clear; close all
Vbi=1; Vp=-2.5; Esat=5e3; L=1e-4;       % V, V, V/cm, cm  (Fig. 15.23 values)
EL=Esat*L; c=Vbi-Vp;
F =@(V,VG) V-(2/3)*((V+Vbi-VG).^1.5-(Vbi-VG)^1.5)/sqrt(c);
f0=-Vp-(2/3)*c*(1-(Vbi/c)^1.5);        % ID0/G0
VGlist=[0 -0.5 -1 -1.5 -2];
hold on
for VG=VGlist
  Phi=@(V) F(V,VG)./(1-sqrt((V+Vbi-VG)/c))-EL;
  VDsat=fzero(Phi,[1e-9, VG-Vp-1e-9]);  % root in (0, VG-Vp)
  IDsat=F(VDsat,VG)/f0;
  VD=linspace(0,2,201); ID=zeros(size(VD));
  for n=1:length(VD)
    if VD(n)<=VDsat, ID(n)=F(VD(n),VG)/f0; else, ID(n)=IDsat; end
  end
  plot(VD,ID)
end
grid on; xlabel('V_D (volts)'); ylabel('I_D/I_{D0}')

(a) Check with the Fig. 15.23 parameters ($V_{bi}=1$, $V_P=-2.5$, $|{\mathcal{E}}_{sat}|=5\times 10^3$ V/cm, $L=1\mu$m, so ${\mathcal{E}}_{sat}L=0.5$ V). Output: $V_G=0$: $V_{Dsat}=0.437$ V, $I_{Dsat}/I_{D0}=0.343$; $V_G=-0.5$: 0.429 V, 0.246; $-1.0$: 0.412 V, 0.162; $-1.5$: 0.377 V, 0.089; $-2.0$: 0.291 V, 0.029. This reproduces the shape of Fig. 15.23: low $V_{Dsat}$ (under 0.5 V), $I_{Dsat}/I_{D0}$ maximum about 0.34 (the plot axis tops at 0.5), slope discontinuity at $V_{Dsat}$.

(b) (Assumed reading.) Use ${\mathcal{E}}_{sat}=-10^4$ V/cm with a long channel (for example $L=100\mu$m, ${\mathcal{E}}_{sat}L=100$ V), and compare with Fig. 15.16. Setting Esat=1e4; L=100e-4 and extending VD to 5 V, the curves converge to the long-channel set of Fig. 15.16: $V_{Dsat}\to V_G-V_P$ (2.5 V at $V_G=0$) and $I_{Dsat}/I_{D0}\to$ the (15.13) values (1.00, 0.61, 0.33, 0.14, 0.035 at $V_G=0,-0.5,-1,-1.5,-2$ V). Decreasing $L$ progressively lowers $V_{Dsat}$ and $I_{Dsat}$ (e.g. ${\mathcal{E}}_{sat}L=5$ V gives $V_{Dsat}=1.85$ V, ratio 0.94; 20 V gives 2.32 V, ratio 0.996).

(c) Where long-channel theory fails. Define failure as $I_{Dsat}/I_{D0}<0.95$ at $V_G=0$. Solving $F(V_{Dsat})/f_0=0.95$ together with the $V_{Dsat}$ equation numerically:

$V_{Dsat}\approx 1.90\text{V},\boxed{{\mathcal{E}}_{sat}L\approx 5.6\text{V}}$

The long-channel theory therefore holds if $|{\mathcal{E}}_{sat}|L\gtrsim 5.6$ V. Examples: $L=5.6/(5\times 10^3)=1.1\times 10^{-3}$ cm $=11\mu$m for $|{\mathcal{E}}_{sat}|=5\times 10^3$ V/cm, and $5.6/10^4$ cm $=5.6\mu$m for $10^4$ V/cm. So channels shorter than about 11 $\mu$m (for $5\times 10^3$ V/cm) or 5.6 $\mu$m (for $10^4$ V/cm) begin to deviate from long-channel behavior.

Values of $I_{Dsat}/I_{D0}$ at $V_G=0$ versus ${\mathcal{E}}_{sat}L$ from the program: 0.5 V: 0.343; 1 V: 0.551; 2 V: 0.767; 3 V: 0.864; 5 V: 0.940; 10 V: 0.983; 20 V: 0.996.