Chapter 14: MS Contacts and Schottky Diodes

The big question of this chapter. Every chip you have ever used has to talk to the outside world through metal wires. At the exact spot where a metal touches a semiconductor, something remarkable happens: electrons have to decide whether to cross freely (an ohmic contact, a good door) or to face a one-way turnstile (a rectifying contact, a Schottky diode). Both behaviours come from one idea: line up the Fermi levels, and see what the bands do.

Think of two reservoirs of water at different heights joined by a pipe. Water flows until the levels match. Electrons do the same thing: they flow from the material with the higher Fermi level to the one with the lower Fermi level until is flat. The piled-up charge left behind builds the barrier. Almost everything in this chapter is that one sentence, dressed up.

The metal-semiconductor (MS) contact appears in every solid-state device. As an ohmic contact it is the link between the semiconductor and the outside world. As a rectifying contact (the Schottky diode or MS diode) it is a device in its own right. The MS diode is a close cousin of the asymmetrical (- or -) step-junction diode, so a large part of the analysis can be borrowed with minor modifications.

Plan of the chapter: (14.1) the equilibrium band diagram of an ideal contact, and how it separates rectifying from ohmic; (14.2) the Schottky diode: electrostatics, -, a.c. and transient response; (14.3) practical complications; (14.4) summary; then the problems.


14.1 Ideal MS Contacts

An ideal MS contact satisfies three assumptions:

  1. Metal and semiconductor are in intimate contact on an atomic scale, with no layer (such as an oxide) between them.
  2. There is no interdiffusion or intermixing of metal and semiconductor.
  3. There are no adsorbed impurities or surface charges at the MS interface.

Ingredients: vacuum level, work function, electron affinity

Fig. 14.1 shows surface-included energy band diagrams of an isolated metal (left) and an isolated -type semiconductor (right), the latter at flat-band (zero field) conditions. The vertical line where the bands end abruptly is the surface. Cross-hatching marks allowed states almost completely filled with electrons.

Figure 14.1 (described). Left: a metal with a filled band up to and a vertical wall whose top ledge is the vacuum level ; the gap from up to is labelled . Right: a semiconductor with , (near because -type), , and the same vacuum level; the gap from to is ; from to is .

Definitions:

  • Vacuum level : the minimum energy an electron needs to free itself completely from the material. Imagine it as the rim of a bathtub: an electron at is just out of the tub.
  • Work function : . It is the energy price for pulling an electron at the Fermi level out of the solid.
  • Metal work function : an invariant property of the metal, from 3.66 eV (Mg) to 5.15 eV (Ni).
  • Semiconductor work function has two pieces:

  • Electron affinity : invariant property of the semiconductor. eV for Ge, Si, GaAs.
  • : computable from the doping (flat-band, bulk value).

Why two pieces? Because the metal’s Fermi level is fixed by the metal, but the semiconductor’s Fermi level moves with doping. Dope more heavily -type and climbs toward , so falls.

Building the equilibrium diagram (, -type)

Thought experiment. Join the two solids so quickly that no electrons have time to move. An instant after contact, the diagram is simply the two isolated diagrams abutted at the interface, aligned to the common (Fig. 14.2(a)). and are material constants and are not altered by contacting.

But . For , lies above . In equilibrium the Fermi level must be position independent (Subsection 3.2.4), so:

  1. Electrons begin to transfer from semiconductor to metal (high to low Fermi level).
  2. The semiconductor loses electrons near the surface, creating a depletion region of uncompensated positive donors.
  3. This builds a growing barrier to further transfer.
  4. The process stops when the transfer rate is the same both ways and is flat.

The result is Fig. 14.2(b). The barrier measured from in the metal up to at the interface is

is the barrier height seen by metal electrons with . Mnemonic: climb from the metal’s Fermi level to the vacuum level (), then drop down to the conduction-band edge ().

Figure 14.2 (described). (a) Instant after contact, : sits below , bands flat, interface abrupt. (b) Equilibrium: flat; semiconductor bands bend upward toward the interface; at the interface is above ; far away . (c) Instant after contact, : above . (d) Equilibrium for : electrons flow metal semiconductor, an accumulation layer forms; bands bend downward toward the interface; no barrier for electrons going semiconductor metal.

Biasing the two structures: who is rectifying?

Conventions (Fig. 14.3(a)): semiconductor grounded, applied to the metal, and when current flows from metal to semiconductor.

Case (barrier type).

  • (Fig. 14.3(b)): is pushed below . The barrier seen by semiconductor electrons shrinks to . An exponentially increasing number of electrons can climb over it: a rapidly rising forward current.
  • (Fig. 14.3(c)): rises above , the barrier for semiconductor electrons grows, and semiconductor-to-metal flow is nearly blocked. Metal electrons still see the same , so a small current flows that is essentially bias independent once exceeds a few : a small, saturating reverse current.

That is rectification, Fig. 14.3(d). The device is the MS diode.

Case .

  • No barrier for electrons going semiconductor metal, so even a small gives a large current.
  • Under reverse bias, metal electrons face a small barrier that vanishes after a few tenths of a volt, so large reverse current appears at small bias, with no saturation.

That is ohmic-like behaviour.

Parallel arguments for a -type semiconductor (Exercise 14.1) give the opposite pattern.

Table 14.1 Electrical nature of ideal MS contacts

-type semiconductor-type semiconductor
RectifyingOhmic
OhmicRectifying

Everything here assumes the contact is ideal; Section 14.3 explains real-world twists.

Anticipated confusion. “Why is the larger metal work function the rectifying one for -type?” A larger means the metal’s Fermi level is deeper below vacuum, so the metal is a thirstier acceptor of electrons; it drains the semiconductor surface and leaves a depleted barrier. For -type the carriers are holes, which float upward in the diagram, so the logic flips.

Exercise 14.1

Problem. (a) Construct the equilibrium band diagram for an ideal -type semiconductor-to-metal contact with . (b) Repeat for . (c) Verify the contact is rectifying for and ohmic-like for . (d) Find the barrier height (from to at the interface) of the rectifying -type contact.

Solution.

(a), (b) The recipe:

  1. Draw the surface-included diagrams of the isolated parts.
  2. Align both to the common and join at the interface.
  3. Without changing the interfacial positions of the semiconductor bands, slide the field-free semiconductor bulk up or down until is constant everywhere.
  4. Connect , , at the interface to the bulk positions.
  5. Erase the construction lines.

Result (described): for the -type semiconductor has low (near ) and is higher, so electrons flow from metal into semiconductor, recombine with holes near the surface and leave ionized acceptors: a depletion layer with bands bending downward toward the interface (a barrier for holes). For holes are pulled into the surface layer, the bands bend upward toward the interface and moves toward (accumulation).

(c) Empty electron states in the metal below (exponentially few) act like holes.

  • : there is a hole barrier in both directions at equilibrium. Raising relative to lowers the barrier for holes going semiconductor metal, so that current grows exponentially with the separation . Reversing the bias blocks it, leaving a small saturating metal semiconductor hole current. Rectifying.
  • : there is no barrier to holes going semiconductor metal, and the small barrier the other way vanishes with a slight downward shift of . Ohmic-like.

(d) Measure the barrier to the valence band at the interface:

Vacuum-level alignment gives and , so . Therefore


14.2 Schottky Diode

Here the semiconductor is taken to be uniformly doped -type, with the polarities of Fig. 14.3(a). The -diode analogies keep the presentation compact.

14.2.1 Electrostatics

Built-in voltage. As in a diode there is a voltage drop across the MS diode at equilibrium. From Fig. 14.4(a) (barrier at the interface; bulk sits above ), the band bending is the difference:

with for an ideal -type contact.

Charge density. Electrons are depleted next to the interface; the depletion region extends a distance into the semiconductor and carries the positive donor charge. Unlike the junction there is no acceptor charge on the other side: the compensating negative charge is an essentially -function sheet of extra electrons in the metal right at the interface (picture the charge on a thin conducting plate). Fig. 14.4(b): a rectangle of height from to and a -spike of negative charge at the interface. Depletion approximation:

Here since the depletion region lies entirely in the semiconductor. Because the charge in the metal is a -function, and const inside the metal, so the metal needs no further attention.

Field. Poisson’s equation in the semiconductor:

Separate variables and integrate from an arbitrary to , where :

The field is negative (it points toward , from the positive donors toward the metal’s negative sheet). Fig. 14.4(c): a straight line from at to zero at . This is identical to the -side field of a - step junction with (Eq. 5.21). The maximum magnitude occurs at the interface:

Potential. Use :

Integrate from to with (the surface-side edge of the semiconductor bulk is the natural reference):

This looks different from the result but is not. In the analysis was set on the far -side; a solution of identical form results if the metal is taken as the reference. With a single semiconductor region, the bulk edge is the preferred reference.

At equilibrium the potential drop across the depletion region is at . With bias, and . (This assumes an ohmic back contact and negligible drop across the neutral bulk.)

Depletion width. Evaluate (14.10) at :

Identical to a - junction.

Exercise 14.2

Problem. Copper is deposited on a carefully prepared -type silicon substrate to make an ideal Schottky diode. eV, eV, , K. Find (a) , (b) , (c) at , (d) at .

Solution.

(a) Ideal -type contact (14.2):

(b) Flat-band position of the Fermi level ( midgap, ):

(c) Put in (14.12):

(d)

14.2.2 - Characteristics

The electrostatics and the general shape of the - curve resemble a diode, but the current mechanism is quite different.

In a - diode (Fig. 14.5(a)) the dominant forward current is recombination in the depletion region at small bias and hole injection from into at larger bias; electron injection into the heavier-doped side is negligible.

In an MS (-type) diode (Fig. 14.5(b)) the recombination and hole-injection currents still exist, but the barrier seen by semiconductor electrons is small, so electron injection from the semiconductor into the metal routinely dominates. It gives a huge forward current long before recombination or hole diffusion matter. Under reverse bias, electron flow from metal into semiconductor (Fig. 14.3(c)) totally dominates; the reverse hole diffusion current and R-G generation current are typically negligible. Since minority carriers play an insignificant role, the MS diode is called a majority carrier device.

The majority-carrier current over the barrier is the thermionic emission current. We derive it for -type, treating first electrons going from semiconductor to metal. Take normal to the interface, directed into the semiconductor.

Step 1: Which electrons can cross? An electron entering the depletion region from the bulk crosses into the metal only if its kinetic energy along exceeds the remaining barrier:

with directed toward the interface (negative).

Step 2: Current from one velocity group. If is the number of electrons per cm with that , then (as in the drift-current derivation of Subsection 3.1.2)

Step 3: Sum over all fast enough electrons.

Step 4: The distribution. For a nondegenerate semiconductor (Maxwell-Boltzmann statistics, integrated over ):

Step 5: Integrate and simplify. Let . The velocity integral is

and . Hence

Using (Eq. 14.3):

is the Richardson constant (first found in the study of electron emission from hot metals).

Step 6: The opposite flow. Metal electrons always see the same barrier , so

At equilibrium the two flows must cancel exactly:

Step 7: Total current.

Combining (14.18) and (14.22):

This is the MS version of the ideal diode equation. For forward bias beyond a few , ; for reverse bias beyond a few , (saturation).

Intuition. looks different from the diode’s because it counts hot-enough majority electrons crossing a barrier, not minority carriers diffusing away. The in the exponent is why a 0.1 eV change in barrier height changes the saturation current by a factor .

Experiment versus theory (Fig. 14.6).

Figure 14.6 (described). (a) Semilog forward versus for an MBR040 diode: a straight line of slope from about 0.1 V to 0.35 V (over many decades of ), with the theoretical diffusion () and R-G dashed curves far below; at higher bias the curve bends over because of series resistance. (b) Reverse characteristic: grows steadily (microamps) as goes from 0 to about V, ending in breakdown.

For V theory and experiment agree almost perfectly (slope close to ). As in the diode, the slope decrease at larger forward bias is due to the voltage drop across the bulk series resistance. In reverse bias there are two departures from ideal:

  1. Breakdown limits the maximum reverse bias. Without edge effects, avalanche breakdown in an MS diode is essentially the same as in an equally doped - or - diode.
  2. The reverse current does not saturate. Unlike a diode this is not R-G current; it is mainly Schottky barrier lowering: decreases slightly with increasing reverse bias,

where is the barrier at zero field at the interface and

( is the surface field, found from the electrostatic relations; with in coulombs and in V/cm the result is in volts, i.e. eV.) Physically, an escaping electron induces an image charge in the metal, and the image attraction plus the applied field rounds off and lowers the top of the barrier. Because , even a small produces a noticeable increase in reverse current. Near avalanche multiplication may further enhance the current.

Exercise 14.3

Problem. Model the V portion of Fig. 14.6(a) as where and are constants ( is the “ideality factor,” unity in Eq. 14.24 but usually slightly above 1). Using the data below, perform a least-squares fit for and .

(V) (A)
0.10
0.15
0.20
0.25
0.30
0.35

Solution logic. Take the log:

This is a straight line with , , slope and intercept . MATLAB’s polyfit(x,y,1) returns [c1, c2] (highest power first), computed by least squares. Then

% Least-squares fit to MS diode I-V data
% ln(I) = ln(Is) + q*VA/(n1*k*T)
I  = [4.047e-7 2.792e-6 1.890e-5 1.263e-4 8.084e-4 4.487e-3];
VA = [0.10 0.15 0.20 0.25 0.30 0.35];
y  = log(I);
c  = polyfit(VA, y, 1);   % least squares; c(1)=slope, c(2)=ln(Is)
slope = c(1);
format compact
n1 = 1/(0.0259*slope)     % kT/q = 0.0259 V
Is = exp(c(2))

Results: .

Quick sanity check by hand: from the end points, over 0.25 V gives slope 37.3 V, so , consistent.

14.2.3 a.c. Response

A small a.c. signal on a d.c. reverse bias causes a charge fluctuation (Fig. 14.7): the depletion width oscillates about its dc value, the donor charge in the semiconductor changes, and the -sheet of electrons at the metal surface changes by the opposite amount. Majority carriers flow quickly in and out of the semiconductor to make this happen. With the charge fluctuation on two planes a distance apart, it is exactly a parallel-plate capacitor:

With (14.12):

Inverting and squaring (14.29):

Figure 14.7 (described). A semiconductor of width with charge, with the small signal shifting the depletion edge in and out, and the compensating charge fluctuating at in the metal.

Reading Fig. 14.8. (a) versus for an MBR040 diode, falling from tens of pF near zero bias to a few pF at V, decreasing more slowly with larger reverse bias. (b) versus is a nearly straight line, as (14.30) predicts (3.4 pF of package stray capacitance was subtracted first). The slope gives , the intercept at gives and, once both are known, (14.3) gives . This is one of the most popular ways to measure barrier heights.

Forward bias is different from a diode. Reverse-bias behaviour mirrors an asymmetric diode, but in forward bias the MS diode’s diffusion current is negligible, so there is little minority carrier injection or storage. Since stored minority carriers give the diffusion admittance, the MS diode has no diffusion capacitance or diffusion conductance. There is still the depletion capacitance, a potentially large parallel conductance , and the series resistance , but even at frequencies approaching or exceeding GHz, and stay frequency independent.

Exercise 14.4

Problem. From the plotted data of Fig. 14.8(b), estimate the barrier height . Take an -type device, cm, room temperature.

Solution.

  1. Intercept of the extrapolated straight line on the axis: V.
  2. Slope of the line: over V:

  1. From (14.30), slope , so

  1. Fermi-level position:

  1. From (14.3):

14.2.4 Transient Response

A very rapid transient response is the signature of the MS diode. In a diode, excess minority carriers stored in the quasineutral regions must be removed before it can switch from forward on-state to reverse off-state (the storage delay). In an MS diode there is almost no minority carrier injection or storage, because the diffusion current is negligible. Typical commercial MS diodes have reverse recovery times of just a few nanoseconds. The response can in fact be limited not by stored charge but by the internal time constant of the junction capacitance and the bulk series resistance. Small-area devices, often called hot carrier diodes, have pF and sub-nanosecond response times.

The Schottky diode clamp (Fig. 14.9). Recall the BJT turn-off discussion of Chapter 12. Connect an MS diode between base and collector of an npn BJT (anode to base, cathode to collector). As the transistor tries to enter saturation during turn-on, the base-collector voltage drops until the MS diode (which conducts at a lower forward voltage than a junction) turns on and diverts the extra base current. The C-B junction stays at a relatively low forward voltage, so very little charge is stored in the BJT, and very little is stored in the Schottky diode. Less charge to remove means a much shorter turn-off time.

Figure 14.9 (described). npn BJT with terminals C, B, E and a Schottky diode symbol across B-C.


14.3 Practical Contact Considerations

14.3.1 Rectifying Contacts

Real MS structures are never quite ideal, even though progress has been made. Silicon devices usually have a thin (5-25 Å) native oxide between metal and semiconductor, which forms almost instantly in air. Arsenic precipitates are believed to form on GaAs surfaces. Allowed electronic states that charge and discharge exist at essentially all semiconductor surfaces. In extreme cases these nonidealities ruin the diode; in modern structures they primarily change the barrier height .

In most real -type diodes , and similarly for -type. In Si, GaAs and most other semiconductors, surface charges tend to pin the equilibrium Fermi level at a specific energy in the surface gap (Fermi-level pinning). Hence the observed varies only slightly with the metal used: for GaAs, regardless of metal, eV (-type) and eV (-type). Since cannot be predicted from and , it must be measured. The - procedure of Exercise 14.4 is one popular technique. All formulas of the previous section still hold if the measured is used.

14.3.2 Ohmic Contacts

Low-impedance contacts, regardless of polarity, are essential in nearly every device. Ideally (-type) and (-type) give ohmic contacts, but Fermi-level pinning means these combinations might still be rectifying. For example, because the surface Fermi level in GaAs is pinned about below , any metal on -type GaAs forms a barrier. So how are ohmic contacts made?

Heavy doping of the surface region beneath the contact (Fig. 14.10(a)): create an layer on -Si before depositing the metal. The reason (Fig. 14.10(b)): the barrier height is to first order unaffected by doping, but the depletion width, hence the barrier width, shrinks with increasing doping (). When the doping exceeds about /cm, carriers can tunnel through the thin top of the barrier (thermionic-field emission); for dopings above about /cm the whole barrier is so narrow that even low-energy majority carriers tunnel through (field emission). The barrier exists but is effectively transparent. (Think of a wall so thin that a ball can quantum-leak through.)

Figure 14.10 (described). (a) Metal on layer on -Si, with SiO on both sides. (b) Three band diagrams, low, moderate and high doping, with arrows showing the emission changing from solely thermionic (over the top) to mostly field emission (through the base).

Heavy doping is seldom the whole story. Annealing is typically required to minimize contact resistance. Aluminum is the most widely used contacting metal for discrete Si devices; heating to about 475 C for a few minutes in lets Al penetrate the native oxide and interdiffuse beneficially with Si. In contacts over shallow - or - junctions, nonuniform Al-Si interdiffusion can drive the Al through the junction and short it: spiking (Fig. 14.11(a)). A small percentage of Si is sometimes added to the Al to inhibit Si diffusion from the substrate and thus the spiking.

Stability under later processing is another concern. Aluminum is unacceptable in complex ICs where steps above 500 C follow contact formation. High-temperature stability comes from the metal-like silicides formed with refractory metals (Mo, Ta, Ti, W). Titanium silicide, TiSi, is widely used: a Ti film over the Si contact area is converted to TiSi by heating in an inert atmosphere. Since Si is consumed, the silicide-silicon interface moves a short distance into the Si, removing surface defects and contamination. The result: a clean, planar, temperature-stable ohmic contact. Fig. 14.11(b) shows the TiSi contact/interconnect metallization typical of modern ICs (a stack of Ti/TiN/Al with a tungsten “plug”).

Figure 14.11 (described). (a) An Al contact on a thin -type layer over Si with an Al spike piercing down through the junction. (b) A cross-section: Si substrate, region with TiSi on top, a tungsten plug in an insulator hole, TiN/Ti liner, and Al interconnect on top.


14.4 Summary

The properties of an ideal MS contact were specified and a method was presented for constructing its equilibrium band diagram. Using different combinations of and , the basic nature of the contacts was probed. Ideally, gives a rectifying contact and gives ohmic behaviour. The rectifying contact, called the Schottky diode or MS diode when used as a device, has electrostatics and reverse-bias a.c. response all but identical to a comparably doped - or - junction. Unlike the diode, the dominant d.c. current is thermionic emission of majority carriers over the barrier, and since the diffusion current is small, the minority carrier injection and storage are also small. Consequently the MS diode has no significant diffusion admittance and switches between on and off states extremely fast. In real Schottky diodes is seldom the ideal value, and the ohmic or rectifying nature may differ from the ideal prediction. An ohmic contact is usually produced in practice by heavy doping of the semiconductor surface region under the contact.


Chapter 14 Problems

Problem information table (difficulty level 1 = easiest, 4 = hardest)

ProblemComplete afterDifficultyPoint weightingShort description
14.114.4110 (1 each part)Quick quiz
14.214.1210 (5 each part)/comb.Draw/use band diagram
14.314.2.128 (2 each part)Parameter computation
14.414.2.128 versus plot
14.514.2.1430 (a-18, b-8, c-4)Auto-draw band diagram
14.614.2.228Confirm Eq. (14.18)
14.714.2.22-315 (a-4, b-5, c-4, d-2)MS photodiode
14.814.2.218Effect of on -
14.914.2.228Injection ratio
14.1014.2.2315 (a-10, b-4, c-1)Schottky barrier lowering
14.1114.2.3212- data analysis
14.1214.2.3420 (a-12, b-6, c-2)Linearly graded MS diode

Problem 14.1 Quick Quiz

(a) MS diode, Schottky diode, hot carrier diode? “MS diode” and “Schottky diode” are two names for the same device: a rectifying metal-semiconductor contact. A “hot carrier diode” is a small-area Schottky diode (with pF) built for sub-nanosecond response; the name refers to the energetic majority carriers that cross the barrier.

(b) Ideal contact with boundary. For an -type semiconductor: ohmic-like if , rectifying if . For a -type semiconductor: ohmic-like if , rectifying if (Table 14.1).

(c) Electrostatics differences? The formulas for , , on the lightly doped side are the same. The differences are: (i) in the MS diode the compensating charge is a -function in the metal rather than a depletion layer on the heavy side, so and ; (ii) the reference is the semiconductor bulk edge; and (iii) is computed from the barrier height instead of the two doping levels.

(d) Dominant current component: thermionic emission of majority carriers over the barrier.

(e) How was found without analyzing metal injection? Metal electrons always see the same barrier regardless of , so is bias independent; at the net current must vanish, so (detailed balance, Eqs. 14.21-14.22).

(f) No diffusion capacitance or conductance: these arise from stored minority carriers injected into the quasineutral regions. In an MS diode the diffusion (minority injection) current is negligible, so there is essentially no minority carrier store.

(g) Fast switching: no minority carrier storage, hence no storage delay; the switching speed is limited only by the time constant of the junction capacitance and series resistance.

(h) Schottky diode clamp: an MS diode connected from base to collector of a BJT. It conducts at a lower forward voltage than the C-B junction and so prevents deep saturation, limiting stored charge and speeding up turn-off.

(i) Practical ohmic contact procedure: heavily dope the semiconductor surface region beneath the contact (making the barrier thin enough for tunneling), deposit the metal (e.g. Al or a silicide such as TiSi), and anneal.

(j) Spiking: nonuniform Al-Si interdiffusion at an Al contact during annealing, with Al penetrating through a shallow junction and shorting it.

Problem 14.2

Assumptions for garbled data. The OCR lost the dopant labels for B, C, D and F. I take: B is -type Ge with ; C is -type Si with ; D is -type Si (as stated); F is -type GaAs with . Use K, eV, and intrinsic-level approximation midgap: (Ge), (Si), (GaAs) cm; eV.

Flat-band formulas ( at midgap):

Combination A (Ge, , , ):

-type with : rectifying; eV. (a) Diagram: bands bend up toward the interface, eV at the interface, eV in the bulk, eV. (b) Argument: lowers , reducing the barrier for semiconductor electrons, giving exponentially growing forward current; raises the barrier and leaves only the small, constant metal-to-semiconductor current rectifying.

Combination B (Ge, , , ):

-type with : ohmic. (a) Diagram: bands bend up toward the interface and approaches or crosses at the surface (hole accumulation); no barrier for holes. (b) Holes flow from semiconductor to metal freely in forward bias; the small barrier for the reverse direction vanishes after a small shift of ; a nonsaturating, ohmic-like characteristic.

Combination C (Si, , , ):

-type, : ohmic. (a) Electrons flow metal semiconductor at contact; accumulation layer; bands bend down toward the interface; at the interface lies below by (specifically eV at the interface). (b) No barrier for electrons; the small barrier for electrons disappears with a few tenths of a volt reverse bias ohmic.

Combination D (Si, , , ):

-type with : rectifying; eV. (a) Diagram: bands bend down toward the interface; at the interface is 0.90 eV, eV in the bulk; eV. (b) Forward bias (metal negative relative to the semiconductor, ) lowers the hole barrier giving exponentially growing hole current; the other polarity leaves a small saturated current rectifying.

Combination E (GaAs, , , ):

-type, : rectifying; eV. (a), (b) as for A: bands bend up, eV, forward bias lowers the barrier.

Combination F (GaAs, , , ):

-type, : rectifying; eV. (a), (b) as for D: bands bend down, eV.

(Note: these are ideal-contact predictions. Section 14.3 explains why measured barriers in GaAs would be pinned near eV () and eV ().)

Problem 14.3

Assumption: (the OCR shows “/cm”; Exercise 14.2 uses the same value). Gold on Si, eV.

(a) eV.

(b) eV, so

(c)

(d)

Problem 14.4

Problem. Plot the equilibrium versus for Si MS diodes at 300 K, with cm (the OCR shows ""; I assume ), for eV.

Solution. At equilibrium

Because increases only logarithmically with , falls nearly as : a straight line of slope about on a log-log plot, with the curves ordered by (larger gives larger ). Numerically, (cm cm/V), so in cm with in volts:

(cm) (eV) (μm),
0.3221.531.912.22
0.2620.560.660.76
0.2020.200.230.26
0.1430.0680.0770.085
% Equilibrium depletion width vs ND in Si Schottky diodes
q=1.6e-19; eps=11.8*8.85e-14; kT=0.0259; ni=1e10; EG=1.12;
ND=logspace(14,17,200);
PhiB=[0.5 0.6 0.7];
for k=1:3
    Vbi = PhiB(k) - (EG/2 - kT*log(ND/ni));   % volts
    W   = sqrt(2*eps*Vbi./(q*ND))*1e4;        % micrometers
    loglog(ND,W); hold on
end
xlabel('N_D (cm^{-3})'); ylabel('W (\mum)');
legend('\Phi_B=0.5 eV','\Phi_B=0.6 eV','\Phi_B=0.7 eV'); grid on

Problem 14.5 Auto-draw band diagram

Logic. Place . For -type with barrier and bulk : . If the contact is not rectifying (ohmic-like), so the program must reject it. The depletion width is , and the potential energy relative to the bulk is (from (14.10), parabola). So for :

and flat beyond . Metal side () is just .

For -type: , with the barrier to at the interface; the bands bend down:

Careful with signs: for -type, bulk and at the surface ; so .

(a)-(c) combined program (silicon default; GaAs by changing the material; or by a flag):

function mscon(PhiB, Ndop, type, mat)
% Equilibrium band diagram of an MS diode.
% PhiB : barrier height (eV)  [n-type: Ec-EF at interface; p-type: EF-Ev]
% Ndop : doping (cm^-3);  type = 'n' or 'p';  mat = 'Si' or 'GaAs'
q=1.6e-19; e0=8.85e-14; kT=0.0259;
switch mat
  case 'Si',   EG=1.12; ni=1e10;  Ks=11.8;
  case 'GaAs', EG=1.42; ni=1.8e6; Ks=13.1;
end
dEF = EG/2 - kT*log(Ndop/ni);        % (Ec-EF) for n, (EF-Ev) for p
Vbi = PhiB - dEF;                     % volts
if Vbi <= 0
    error('Vbi<=0: contact is not rectifying. Choose a larger PhiB.');
end
W  = sqrt(2*Ks*e0*Vbi/(q*Ndop));      % cm
xm = linspace(-0.5*W, 0, 20);         % metal side
xs = linspace(0, W, 100);             % depletion region
xb = linspace(W, 1.5*W, 20);          % neutral bulk
x  = [xm xs xb]*1e4;                  % micrometers
Vs = Vbi*(1-xs/W).^2;                 % band bending (eV)
if type=='n'
    Ec = [PhiB*ones(size(xm)), dEF+Vs, dEF*ones(size(xb))];
    Ev = Ec - EG;  Ei = Ec - EG/2;
else
    Ev = -[PhiB*ones(size(xm)), dEF+Vs, dEF*ones(size(xb))];
    Ec = Ev + EG;  Ei = Ev + EG/2;
end
% inside the metal the semiconductor bands do not exist: blank them
Ec(x<0)=NaN; Ev(x<0)=NaN; Ei(x<0)=NaN;
plot(x,Ec,'b',x,Ev,'b',x,Ei,'b--',[min(x) max(x)],[0 0],'r'); hold on
xlabel('x (\mum)'); ylabel('Energy (eV), E_F = 0');
title(sprintf('%s %s-type MS diode, \\Phi_B=%.2f eV, V_{bi}=%.3f V, W=%.3f \\mum',mat,type,PhiB,Vbi,W*1e4));
text(min(x),0.05,'E_F');
end

Example calls: mscon(0.62,1e16,'n','Si') reproduces Exercise 14.2 ( V, m); mscon(0.95,1e16,'n','GaAs') gives a GaAs diode with pinned barrier.

Problem 14.6 Derivation of Eq. (14.18)

Problem. Accept (14.16) and (14.17); fill in the steps leading to (14.18).

Solution.

Start:

Pull out the constants:

Write . The velocity integral is an exact differential: , so

With : . Then

The two minus signs combine to a positive result. Simplify the prefactor:

Now the exponent. From (14.14), , so . Combining exponentials:

By (14.3), . Therefore

with A/cmK. This is (14.18).

Problem 14.7 MS Photodiode

(a) Short circuit. With the terminals shorted, and the band diagram equals the equilibrium diagram (bands bent up toward the interface, of bending). Electron-hole pairs created in the depletion region, and minority holes created within a diffusion length of its edge that diffuse into it, are swept apart by the built-in field: electrons slide down the potential into the neutral bulk (toward ), holes slide toward the metal (toward the interface), where they recombine with the metal’s electrons. Net conventional current flows from the semiconductor toward the metal. With the polarity convention of Fig. 14.3(a) ( from metal to semiconductor), the short-circuit photocurrent is negative: .

(b) Open circuit. Now the total current must be zero. The photocurrent (holes to the metal, electrons to the bulk) charges the semiconductor positively relative to the metal, i.e. it builds a photovoltage across the contact (metal positive relative to semiconductor in the sense of forward bias). That reduces the band bending to , so the semiconductor Fermi level sits above the metal’s, and the barrier for semiconductor electrons shrinks until the forward thermionic emission current exactly cancels the photocurrent. Diagram: at the interface unchanged (set by the metal and surface), bulk lowered by relative to equilibrium, below the semiconductor quasi-Fermi level by ; bands partially flattened. The form follows from zero total current: forward injected current photocurrent.

(c) Photocurrent. By the simplified procedure of Subsection 9.2.1, the photocurrent is the generation rate times the volume of the “collecting” region: carriers generated within the depletion region and within one minority-carrier diffusion length of its edge are collected. Minority carriers in the -type semiconductor are holes, and the metal side contributes none, so (low-level injection, uniform generation , area ):

where the negative sign follows the Fig. 14.3(a) polarity. Total current:

(Compared with the photodiode, the term is absent because there is no quasi-neutral minority-carrier region on the metal side.)

(d) Sketch. The illuminated - curve is the dark diode curve shifted downward by (slightly bias dependent through ): it crosses the axis at (I=0), and passes through at . The fourth quadrant (, ) is where power is delivered, as in a solar cell. This agrees with (a) (negative at ) and (b) (positive where ):

Problem 14.8 Effect of series resistance

Problem. Plot the forward - for , V, A.

Assumption: the OCR shows ” A”, the saturation current’s exponent is lost. I take A, which makes the curve span the requested ranges (at A: V).

Solution. The applied voltage is the junction voltage plus the resistor drop:

So solve explicitly for as a function of :

Is=1e-10; Vt=0.0259;
I=logspace(-9,-1,400);
Rs=[0 0.1 1 10];
for k=1:4
    VA = Vt*log(I/Is+1) + I*Rs(k);
    semilogy(VA,I); hold on
end
axis([0 0.6 1e-9 1e-1]); grid on
xlabel('V_A (V)'); ylabel('I (A)');
legend('R_S=0','0.1 \Omega','1 \Omega','10 \Omega')

Result: for a straight line of slope (one decade per 59.6 mV). The series resistance pushes the curves to the right by , which becomes significant only when , i.e. . With the curve bends over beyond mA and at mA is displaced by 0.1 V; with the bend is near 30 mA; with near 0.3 A (beyond the plotted range, so almost indistinguishable from ideal). At high current the characteristic becomes an ohmic straight line .

Problem 14.9 Minority carrier injection ratio

Problem. Estimate for Si with A/cmK, eV, cm, s, K.

Solution. Both currents scale as , so the ratio is bias independent and equals the ratio of the saturation current densities.

Thermionic emission:

Diffusion (equated to a wide-base - diode):

Take cm/V-s at (assumption; the problem does not give it):

Evaluate the factors: cm/s and cm; so

Ratio:

So for roughly every two million majority electrons injected into the metal, only about one hole is injected into the semiconductor: the MS diode is truly majority-carrier.

Problem 14.10 Schottky barrier lowering

Assumptions: cm (OCR garbled; consistent with the Fig. 14.6 diode, ) and V (the value found in Exercise 14.4).

(a) Surface field (from (14.7) at with ):

Selected values:

(V) (V/cm) (V)
00.02291
0.02921.27
0.04692.5
0.06936.0

Sample computation at V: V/cm; V.

q=1.6e-19; eps=11.8*8.85e-14; ND=1e16; Vbi=0.6; Vt=0.0259;
VA=linspace(-50,0,300);
Es=sqrt(2*q*ND*(Vbi-VA)/eps);           % V/cm
dPhi=sqrt(q*Es/(4*pi*eps));             % V
figure(1); plot(VA,dPhi); xlabel('V_A (V)'); ylabel('\Delta\Phi_B (V)');
ratio=exp((dPhi-dPhi(end))/Vt);         % I_S(VA)/I_S(0)
figure(2); plot(VA,ratio); xlabel('V_A (V)'); ylabel('I(V_A)/I(0)');

(b) Since , the reverse saturation current relative to its zero-bias value is

(the factor once V). The values are in the table column above, from 1 at to 6.0 at V.

(c) is small (tens of millivolts, a few percent of ) but because of the exponential dependence on it makes the reverse current rise by a factor of several over the reverse range: the non-saturation seen in Fig. 14.6(b). The lowering grows as , so it rises fast at first and then slowly, consistent with the slow steady creep of the measured reverse current.

Problem 14.11 - data analysis

Problem. Least-squares fit of Table P14.11 for , , , with cm. In the table the column is in units of (this scaling is the one consistent with the slope used in Exercise 14.4).

(V) ( F)
1.090.953
2.081.494
3.072.035
4.062.579
5.053.125
6.043.673
7.034.217
8.024.763
9.015.320
10.005.890

Solution. Per (14.30), : a line with , , .

Least-squares sums (): , , , .

Results: V, cm, eV, agreeing within a few percent with the graphical estimates of Exercise 14.4 ( V, , eV).

VA = -[1.09 2.08 3.07 4.06 5.05 6.04 7.03 8.02 9.01 10.00];
y  = [0.953 1.494 2.035 2.579 3.125 3.673 4.217 4.763 5.320 5.890]*1e21;
c  = polyfit(VA, y, 1);          % y = c(1)*VA + c(2); slope is negative
m  = -c(1);  Vbi = c(2)/m
q=1.6e-19; eps=11.8*8.85e-14; A=1.5e-3; kT=0.0259;
ND = 2/(q*eps*A^2*m)
PhiB = Vbi + (0.56 - kT*log(ND/1e10))

Problem 14.12 Linearly graded MS diode

Problem. in the semiconductor ( constant). (a) Derive . (b) How is determined? (c) Find the junction capacitance.

(a) Solution. Depletion approximation: for , zero beyond.

Poisson, with :

(Parabolic, maximum magnitude at the interface.) The potential with :

Check: . At , :

(b) Built-in voltage. where is the Fermi-level position in the neutral semiconductor at the edge of the depletion region, where (the doping is not uniform, so there is no single bulk value):

This is a transcendental pair in (the same self-consistency as in the linearly graded junction, Subsection 5.2.5); solve it by iteration: guess , compute , update with the logarithm, repeat until convergence. (The log varies slowly, so it converges in a few passes.)

(c) Capacitance. per (14.28), so

Thus : a plot of versus is a straight line, whose slope gives and whose intercept gives .


Part II Supplement and Review

Part II was a long tour of junction devices: the diode (static, a.c., transient), its special relatives (solar cells, LEDs, --, varactors), the BJT, the PNPN family, heterojunctions, and finally the MS contact. This closing section gives a reading list, a glossary to test yourself against, and three problem sets that require integrated knowledge of Chapters 5-11, with fully worked solutions.

Alternative / Supplemental Reading List

Author(s)Type (A = alternative, S = supplemental)LevelRelevant chapters
StreetmanAUndergraduate5-7, 11
NeamenAUndergraduate7-10
TyagiA/SAdvanced undergraduate, introductory graduate6-10, 12-14, 18
NavonAUndergraduate12 (PNPN)
SahSUndergraduate to graduate (variable)7 (BJT, HBT and PNPN)
YangA/SUndergraduate3 ( electrostatics), 6 (BJT technology), 7 (MS diodes)

Books: (1) D. H. Navon, Semiconductor Microdevices and Materials, Holt, Rinehart and Winston, 1986. (2) D. A. Neamen, Semiconductor Physics and Devices, Basic Principles, Irwin, 1992. (3) C. T. Sah, Fundamentals of Solid-State Electronics, World Scientific, 1991. (4) B. G. Streetman, Solid State Electronic Devices, 4th ed., Prentice Hall, 1995. (5) M. S. Tyagi, Introduction to Semiconductor Materials and Devices, Wiley, 1991. (6) E. S. Yang, Microelectronic Devices, McGraw-Hill, 1988.

Figure Sources / Cited References

(1) S. M. Sze, Physics of Semiconductor Devices, 2nd ed., Wiley, 1981. (2) C. T. Sah, R. N. Noyce and W. Shockley, “Carrier Generation and Recombination in P-N Junctions and P-N Junction Characteristics,” Proc. IRE, 45, 1228 (1957). (3) D. K. Schroder, Semiconductor Material and Device Characterization, Wiley, 1990. (4) R. H. Kingston, “Switching Times in Junction Diodes and Junction Transistors,” Proc. IRE, 42, 829-834 (1954). (5) R. H. Dean and C. J. Neuse, “A Refined Step-Recovery Technique for Measuring Minority Carrier Lifetimes and Related Parameters in Asymmetric p-n Junction Diodes,” IEEE Trans. Electron Devices, ED-18, 151-158 (March 1971). (6) E. S. Yang, Microelectronic Devices, McGraw-Hill, 1988, p. 383. (7) M. A. Green et al., “Characterization of 23-Percent Efficient Silicon Solar Cells,” IEEE Trans. Electron Devices, 37, 331-336 (Feb. 1990). (8) Photovoltaics: Program Overview Fiscal Year 1992, NREL, DOE/CH10093-190, March 1993. (9) M. G. Craford, “LEDs Challenge the Incandescents,” IEEE Circuits and Devices, 8, 24-29 (Sept. 1992). (10) M. G. Craford, “Recent Developments in Light-Emitting-Diode Technology,” IEEE Trans. Electron Devices, ED-24, 935-943 (July 1977). (11) BiCMOS technology, Solid State Technology, 35, 33 (Oct. 1992); see also the special series on BiCMOS processing edited by D. Gupta and M. T. Bohr, begun in Solid State Technology, June 1992. (12) M. Lundstrom, “III-V Heterojunction Bipolar Transistors,” Ch. 1 in Heterojunction Transistors and Small Size Effects in Devices, ed. M. Willander, Studentlitteratur and Chartwell Bratt, 1992. (13) I. R. C. Post, P. Ashburn and G. R. Wolstenholme, “Polysilicon Emitters for Bipolar Transistors: A Review and Re-Evaluation of Theory and Experiment,” IEEE Trans. Electron Devices, 39, 1717 (July 1992). (14) For MBE, consult the device fabrication references in the R1 mini-chapter. (15) S. Tiwari and D. J. Frank, “Empirical Fit to Band Discontinuities and Barrier Heights in III-V Alloy Systems” (title partly illegible in the OCR). (16) Navon, 1986, pp. 410-411. (17) Sze, 2nd ed., 1981, pp. 255-256.

Review List of Terms

Defining these in your own words is a rapid review of Part II. Concise definitions follow so you can check yourself.

Junction diode basics (1-17)

#TermMeaning
1wide-base diodeQuasineutral widths minority-carrier diffusion lengths; the classic ideal diode.
2narrow-base diodeQuasineutral widths diffusion lengths; minority profiles are straight lines, not .
3ideal diodeObeys : no R-G in depletion region, low-level injection, no other processes.
4law of the junctionMinority concentration at the depletion edge: .
5quasineutral regionRegion outside the depletion region where , small.
6breakdownSudden large reverse current at .
7impact ionizationA carrier gains enough energy from the field to knock a bound electron free, creating an electron-hole pair.
8avalanchingRepeated impact ionization chain reaction.
9multiplication factor, ratio of the multiplied current to the unmultiplied current.
10Zener processBreakdown by direct band-to-band tunneling in very narrow junctions.
11tunnelingQuantum penetration of a thin barrier.
12conductivity modulationLarge injected carrier densities raise the conductivity of the lightly doped region (high-level injection).
13punch-through (narrow-base diode)Depletion region reaches the end of the narrow region, so breakdown or current limiting occurs earlier.
14high-level injectionInjected minority concentration comparable to or exceeding the majority doping.
15quasistaticSignals vary slowly enough that the device follows the d.c. characteristics.
16hyperabruptDoping profile with doping decreasing away from the junction, giving a steeper -.
17varactorDiode designed as a voltage-variable capacitor.

Capacitance and transients, optoelectronics (18-37)

#TermMeaning
18abruptStep doping profile.
19profilingDeducing from - data ( slope).
20junction capacitanceDepletion-layer capacitance, .
21diffusion admittanceSmall-signal admittance from stored minority carriers in forward bias ( and ).
22turn-off transientSwitching from forward to reverse bias.
23storage delay time ()Time during which stored charge is being removed and the current stays at .
24reverse recovery timeTotal time until the current falls to a specified fraction of .
25reverse injectionMinority carrier injection in the reverse direction when the stored charge flows back.
26step recovery diodeDiode with a very abrupt end of the storage phase, used for pulse sharpening.
27photodetectorDevice that converts light to an electrical signal.
28solar cell junction delivering power from light in the fourth quadrant.
29LEDForward-biased direct-gap diode emitting photons by radiative recombination.
30-- diodeDiode with an intrinsic layer between and , wide depletion region, fast, low capacitance.
31avalanche photodiodePhotodiode operated near breakdown to multiply photocurrent.
32fill factor, how “square” the solar cell’s - is.
33shadowingLoss from the metal grid blocking light.
34texturingRoughened surface that reduces reflection and traps light.
35concentrator solar cellsCells used with lenses or mirrors to focus sunlight.
36isoelectronic trapImpurity of the same valence that traps carriers and enhances radiative recombination in indirect-gap LED materials (e.g. N in GaP).
37total internal reflectionLight striking a boundary beyond the critical angle stays inside the high-index semiconductor, limiting LED extraction.

BJT (38-68)

#TermMeaning
38BJTBipolar junction transistor.
39emitter, base, collectorThe three regions: emitter injects carriers, base transports them, collector collects.
40common baseBase is common to input and output.
41common emitterEmitter is common; amplifier configuration.
42active modeE-B forward, C-B reverse.
43saturation modeBoth junctions forward.
44cutoff modeBoth junctions reverse.
45inverted modeE-B reverse, C-B forward (roles reversed).
46buried layerHeavily doped layer beneath the collector to lower collector resistance in ICs.
47quasineutral base width minus depletion encroachment.
48emitter efficiency, fraction of emitter current that is carriers injected into the base.
49base transport factor, fraction of injected carriers reaching the collector.
50common base d.c. gain (to first order).
51common emitter d.c. gain.
52performance parameters and related figures of merit.
53Ebers-Moll equations/modelSuperposition of two coupled diodes describing all modes.
54forward gainGain in the normal (active) direction.
55base-width modulationChange of with collector voltage.
56Early effectOutput conductance caused by base-width modulation.
57punch-through (BJT)Base fully depleted so the C-B depletion region touches the E-B region.
58regenerativePositive feedback process (as in the SCR two-transistor model).
59phototransistorBJT whose base current comes from light.
60intrinsic transistorThe active part of the BJT excluding parasitics.
61base series resistanceResistance of the lateral base path.
62current crowdingEmitter current concentrates at the edge due to the base resistance drop.
63graded baseBase doping decreasing from emitter to collector, producing a built-in field that speeds carriers.
64Gummel plot and versus .
65BiCMOSTechnology integrating bipolar and CMOS.
66shallow emitterVery thin emitter for high-speed devices.
67polysilicon emitterPolycrystalline Si emitter giving high .
68HBTHeterojunction bipolar transistor.

Heterojunctions, BJT dynamics, PNPN, MS contacts (69-100)

#TermMeaning
69heterojunctionJunction between two different semiconductors.
70band alignmentThe relative positions of the band edges across a heterojunction.
71lattice-matchedMaterials with equal lattice constants, giving defect-free interfaces.
72graded junction (HBT)Composition gradually changed across the junction to remove band spikes.
73Hybrid-pi equivalent circuitSmall-signal BJT model with , , , , .
74transconductance.
75base transit timeAverage time for carriers to cross the base, .
76rise, storage delay, fall timesThe three stages of the BJT switching waveform.
77Schottky diode clampMS diode from base to collector preventing saturation.
78thyristorsFour-layer switching devices.
79SCRSilicon controlled rectifier.
80anode, cathode, gateThe three SCR terminals.
81blocking voltagesMaximum forward and reverse voltages without conduction.
82two-transistor modelAn SCR as a and an connected in a regenerative loop.
83GTO SCRGate turn-off thyristor.
84LASLight-activated switch (light-triggered SCR).
85 burnoutOverheating from too fast a current rise at turn-on.
86 effectFalse triggering from fast voltage rise via capacitive charging current.
87DIAC, TRIACBidirectional triggering diode and bidirectional triode thyristor.
88PUTProgrammable unijunction transistor.
89Schottky diodeRectifying MS diode.
90vacuum levelEnergy of a free electron at rest just outside the solid.
91metal work function.
92electron affinity at the semiconductor surface.
93thermionic emissionEmission of carriers over a barrier due to thermal energy.
94Richardson’s constant.
95Schottky barrier loweringReduction of with field due to image force.
96hot carrier diodeSmall-area, very fast Schottky diode.
97Fermi-level pinningSurface states fix at the surface, making nearly independent of the metal.
98field emissionTunneling through a thin barrier.
99Al spikingAl penetration through a shallow junction.
100silicideMetal-silicon compound used for stable ohmic contacts.

Part II: Review Problem Sets and Answers

These sets assume knowledge, at times integrated, of Chapters 5-11. Set A is adapted from a one-hour open-book exam; Sets B and C combine select problems from closed-book exams. Answers to Sets A and B are given at the end; Set C has no published answers (so it can serve as homework), but a worked solution is provided here for completeness.


Problem Set A

Problem A1

A junction has the doping profile sketched: for (equal magnitude on both sides), for , and for . In the entire problem the carrier concentrations may be neglected (, ) in the region.

(Figure described: versus : a step down to on the left, zero between and , and for . This is effectively a -- structure with equal-magnitude doping and a thin “intrinsic” spacer.)

(a) Built-in voltage? Following Subsection 5.1.4, , the ratio of electron concentrations deep in the two neutral regions. Deep in the -side, ; deep in the -side, . So

Justification: the built-in voltage depends only on the carrier concentrations in the neutral regions on each side (equivalently the Fermi-level position relative to the band edges there), not on the profile in between.

(b) Charge density (depletion approximation). for ; for (no dopants, no carriers); for ; elsewhere. The sketch is two equal-height rectangles of opposite sign separated by a gap of width .

(c) Electric field. Poisson: . With :

For :

At : .

For : , so the field is constant:

For (integrate from to where ):

The sketch: a negative-going straight line from zero at down to at , a flat plateau up to , then a straight line rising back to zero at .

(d) Relation between and . The positive and negative charge areas must be equal:

Equivalently, continuity of at : , the same result. (In a standard step junction with this gives ; here the central region merely adds the spacer.)

(e) Equilibrium band diagram. is flat. Far left: below by (-side); far right: above by the same amount. Bands curve (parabola, since is linear) on , run as a straight line (constant slope, constant field) for , and curve again (opposite concavity) on , with total bending . The only difference from a simple step junction () is the constant-slope straight-line segment in . The diagram is symmetric about the midpoint of the spacer, since for .

Problem A2

Two Si - diodes at 300 K are identical except for -side doping: diode #1 has cm, diode #2 has cm.

(a) Larger ? Diode #2. . The side term is the same for both; is larger for the heavier-doped diode, so . (Heavy doping on the side is a hint that cannot be used blindly: the side may be degenerate, so the Fermi-level construction is the safe route.)

(b) Larger ? Diode #1. Avalanche breakdown on the lightly doped side scales roughly as : V for cm, but about 60 V for cm (typical Si values).

(c) Larger at a given reverse bias ? Diode #2. , with

Thus (smaller ) and .

(d) Larger if ideal, reverse bias beyond a few volts? Diode #1. The ideal reverse current is

Now . Also and decreases with doping, so ; with equal , so is also larger for #1. Both factors favour .

(e) Larger if the diodes are not ideal (real Si at 300 K, reverse bias beyond a few volts)? Diode #1. The reverse current is dominated by R-G generation in the depletion region:

With (trap density, same in both diodes since only the doping differs), is the same. But from (c), so .

(f) Larger diffusion capacitance at a given forward bias? Diode #1. In the ideal region, ; more precisely with at a given forward bias, and , which is larger for diode #1 by (d). With equal , .

(g) Larger storage delay time for the same ? Same for both. The approximate solution (Eq. 8.8) (or the more accurate (8.9)) depends only on and . The ratio is given as the same; , and hence , is inferred to be the same in both diodes since only is different. Hence .

Problem A3

(a) Inverted-mode carrier activity in a BJT. The given diagram (active mode) shows holes injected from the heavily doped emitter () across the base to the collector. In the inverted mode the junction biases are interchanged: the original collector-base junction is forward biased and the original emitter-base junction is reverse biased. The diagram: Fermi level flat apart from the junction offsets; the “collector” (now acting as emitter, lightly doped ) injects holes into the base; they diffuse across the base, and are collected by the reverse-biased original emitter. The injected hole flow is therefore from the right () to the left () in the drawing. A caution to avoid misinterpretation: the carriers still diffuse “downhill” in concentration, but the roles are exchanged, and because the lightly doped collector is a poor injector, a large share of the forward-biased junction current is electron injection from base into the collector (a wasted, base-current component).

(b)(i) Why lower gain in backward connection. The gain is limited by emitter efficiency . In the proper connection the E-B junction has , so hole injection into the base dominates over electron injection into the emitter, . In the backward connection the injecting junction is the C-B junction, where : electron injection from base into collector becomes significant, so the injection efficiency is far below that of the real emitter, degrading and with it .

(b)(ii) Why greater sensitivity to base-width modulation. The larger depletion region sits at the reverse-biased junction, extending mainly into the more lightly doped side. In the proper connection the reverse-biased C-B junction has , so most of the depletion layer extends into the collector, only slightly altering . In the backward connection, the reverse-biased junction is the E-B one with , so most of the depletion region extends into the base. Much larger changes of result for equivalent bias changes.


Problem Set B

Problem B1

A diode has with constants (negative for , positive for , vanishing at and saturating at on the left).

(a) Depletion approximation, in a sentence. (i) and are much less than in a region about the metallurgical junction, so there; (ii) elsewhere (neutral regions).

(b) Charge density. in : negative for (value at , saturating toward for large ), zero at , and growing exponentially positive up to ; zero beyond and below (abrupt edges).

(c) Electric field. With :

(d) Completing the electrostatics (organized steps).

Step 1. Solve for the potential in the depletion region using with at :

Step 2. Impose two boundary conditions at the right edge: and . These two equations contain three unknowns, , and (for a given ); once is known they can be solved simultaneously for and , giving . In this problem the solution must be obtained numerically (transcendental equations).

Step 3. Obtain by a procedure paralleling the linearly graded junction analysis of Subsection 5.2.5: follows from the Fermi-level position in the neutral regions at the depletion-region edges (using evaluated at and ), which depends on the unknown , so Steps 2 and 3 are solved self-consistently.

Problem B2

The band diagram of a Si step junction at room temperature (described, because it is not legible): the quasi-Fermi levels in the far regions are labelled so that is the applied reverse voltage, on the -side and on the -side in the neutral regions. Given: cm, cm, s, , cm/V-s, , F/cm, cm, V.

Reading of the data: the ratio of the OCR-ed quantities (e.g. the R-G current of A in the key) requires s, which agrees with the lifetime used in part (d).

(a) Reverse bias magnitude. The difference of the Fermi levels in the neutral regions equals :

Explanation: the diagram shows the -side Fermi level above the -side Fermi level by , the separation of Fermi levels being the applied voltage across the diode (). The reverse bias is 0.56 V.

(b) Built-in voltage. From the equilibrium positions, :

(c) R-G current (reverse bias, ):

(d) Diffusion current. First the doping: :

Diffusion constants and lengths:

(The widths the quasineutral extent in a wide-base diode, so the wide-base formula applies.) Under reverse bias the ideal-diode current is the saturation current with a negative sign:

Evaluate the bracket: and . The prefactor is . Combining:

The diffusion current is some 500 times smaller than the R-G current, as is typical of Si at room temperature.

(e) Junction capacitance.

(f) Minority carrier plot (linear scale). Under reverse bias the minority concentrations at the depletion edges fall to essentially zero (law of the junction with ): , . Far away they recover to the equilibrium values cm and cm over distances of order (left) and (right). Since , the electron deficit on the -side extends farther than the hole deficit on the -side. The sketch: two exponential rises from near zero at the edges to the (tiny) equilibrium level, the left one stretched out longer.

(g) Significant diffusion capacitance? No. comes from stored excess minority carriers adjacent to the depletion region; under reverse bias there is a deficit, not a store.

(h) Storage delay for a pulse to larger reverse bias? No. The diode is already reverse biased before the pulse and has no stored minority-carrier charge to remove; the current merely adjusts quickly (with the charging of ).

Problem B3

Two Si BJTs are identical except . and in both, active mode at the same bias.

(a) Larger emitter efficiency? BJT #2. With the quasineutral base width under the same biasing,

so : a wider base gives a larger electron back-injection term, hence lower efficiency.

(b) Larger base transport factor? BJT #2.

so . Physically, fewer carriers recombine while crossing the narrower base.

(c) Larger ? BJT #2. increases monotonically with , and both factors are larger for #2.

(d) Greater sensitivity to base-width modulation? BJT #2. A given bias change produces the same in both. Sensitivity is the fractional change , which is larger for the narrower base: .

(e) Larger punch-through voltage? BJT #1. Punch-through occurs when the C-B depletion region consumes the whole base. For the same per volt, completely depleting the wider base of #1 requires a larger .

If the maximum output current is limited by carrier multiplication and avalanching:

(f) Larger ? Same for both. equals the avalanche breakdown voltage of the C-B junction, which depends on the junction dopings (identical in the two transistors).

(g) Larger ? BJT #1. From Eq. (11.54),

by (c), so .


Problem Set C (no published answers; worked solutions supplied)

Problem C1

(a) Which assumption is not invoked in deriving the ideal diode equation? (iii) Narrow-base diode. The derivation assumes a wide-base diode (quasineutral widths much greater than the diffusion lengths); (i) no R-G in the depletion region, (ii) low-level injection, and (iv) no other processes are all invoked.

(b) Dominant current in most Si diodes at room temperature under reverse and small forward bias? (ii) The R-G current. (The ideal diffusion current is far smaller in Si at 300 K because is small.)

(c) Which statement is incorrect? (iv). Breakdown in a diode is reversible provided the power is limited (so (i) is true), the Zener effect needs very narrow depletion regions cm (ii true), and roughly for avalanching (iii true). Statement (iv) as printed, that avalanching dominates when V, is reversed: below about 4.5 V (heavy doping, narrow depletion) the Zener (tunneling) process dominates; avalanching dominates for larger breakdown voltages. (The OCR of (iv) is garbled; I reconstructed it from the usual textbook statement.)

(d) Which statement about the junction capacitance is correct? The OCR dropped (i) and (ii). Statements (iii) ” vanishes under forward biasing” and (iv) ” is associated physically with fluctuations in the minority carrier concentrations at the edges of the depletion region” are both false: does not vanish in forward bias (it grows), and it is associated with fluctuations in the majority-carrier charge at the depletion edges. The correct statement is therefore one of the first two, which in the usual version reads “the magnitude of decreases with increasing reverse bias” (assumption, since it is the standard property: ).

Problem C2

Figure described and assumption stated. The linear plot shows in two - diodes with the same and : both curves start at the depletion-edge value (marked , above the equilibrium level ) and decay with the same diffusion length to the same equilibrium level; Diode A has the higher edge value. Low-level injection prevails.

(a) (i) forward biased: the minority concentration at the edge exceeds the equilibrium value (law of the junction), which happens only under forward bias.

(b) (iii) smaller than: , and Diode B’s edge value is lower, so .

(c) (iii) significantly smaller than: the current is proportional to the slope at the edge, , which is lower for B (exponentially smaller for a slightly smaller bias).

(d) (ii) roughly the same as: depends mostly on the (equal) on the lightly doped side, not on the applied forward bias.

(e) (iii) essentially the same for both: with identical (same decay length implies same ) and the same , is the same.

Problem C3

Assumed figure. A log plot of carrier concentrations versus : flat majority levels and in the neutral regions; the minority levels and rise above their equilibrium values and at the depletion-region edges and and decay away from the junction; all minority values remain far below the majority levels.

(a) Forward or reverse biased? Forward biased: the minority concentrations at the depletion edges are larger than the equilibrium values (excess carriers, piled up), as predicted by the law of the junction with . In reverse bias they would fall below equilibrium.

(b) Low-level injection? Yes: even the elevated minority concentrations , are far below the majority levels , on the log plot, so the majority concentrations are not perturbed.

(c) Link between minority pile-up and . The diffusion capacitance measures the change in stored minority carrier charge with applied voltage, . A larger pile-up near the edge means more stored charge, and since the pile-up grows exponentially with , is proportional to the stored charge (about ).

(d) Link between the pile-up and . At turn-off, the stored excess minority carriers must be removed (swept out by the reverse current and by recombination) before the junction can become reverse biased. The larger the store, the longer the current stays pinned at : grows with the stored charge (with and ).

Problem C4

Setup. Given sketched characteristics of a - Si step junction at room temperature: reverse - (small, slowly rising magnitude, R-G dominated), - (decreasing as ), and the turn-off current (plateau at for then decay). Draw dashed curves on each (verbal description of what to draw):

(a-c) doubled.

(a) -: reverse current is dominated by R-G, , so the dashed curve lies lower by a factor of about and keeps the same slow rise. (The ideal saturation component would also fall, roughly by 2, but it is negligible.)

(b) -: , so the dashed curve is higher by about , with the same shape (a slight additional change through ).

(c) : no effect to first order; depends on and , which are unchanged.

(d-f) and doubled.

(d) -: , so the dashed reverse-current curve is lower by a factor of 2 (the diffusion current changes only as , negligible in comparison).

(e) -: no effect ( depends only on , and ).

(f) : the storage plateau at becomes longer: doubles (the plateau level and are set by the circuit, so they stay the same), and the subsequent recovery tail also lasts longer.