part04

Chapter 4: Basics of Device Fabrication

Reading note. This is a “read-only” chapter in Pierret’s scheme: qualitative, a handful of equations, no computer exercises and no end-of-chapter problems, and nothing from it appears in the Review Problem Sets. So there is nothing to solve here. In place of problems I give a few small worked illustrations (marked as such) that use the chapter’s few equations, so you can feel their size. Put down your pencil, as the author says, and listen to the story of how a sand-derived crystal becomes a computer.

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Introduction: why a physics course visits the factory

Imagine you must analyse a violin without ever having seen one being built. You could write down the wave equation for a vibrating string and still be baffled that the instrument’s voice depends on the varnish, the wood’s grain and the thickness of the top plate. Devices are the same. The equations of Chapters 1-3 describe ideal crystal and carriers, but a real diode has a particular doping profile, a particular oxide thickness and a particular metal contact, and each of those is a consequence of how it was made. Knowing the fabrication steps tells you which simplifications (“the doping is uniform”, “the junction is abrupt”, “the oxide is perfect”) are honest and which are fibs.

The chapter proceeds in three moves:

1. Building-block processes (Section 4.1): oxidation, diffusion, ion implantation, lithography, thin-film deposition, epitaxy. Think of these as the six verbs of chip making: grow, spread, shoot, print, coat, extend.
2. Sequencing them (Section 4.2): first into a simple $pn$ junction diode, then into a real CPU process (Intel’s CHMOS).
3. Summary (Section 4.3).

The same verbs are repeated, in different orders, dozens of times for a modern IC. Like a cook with six techniques and thousands of recipes.

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4.1 Fabrication Processes

4.1.1 Oxidation

Why silicon won. Silicon’s dominance is partly an accident of chemistry: its native oxide, silicon dioxide ($\mathrm{Si}{\mathrm{O}}_2$), is easy to make, mechanically tough, an excellent electrical insulator, and bonds to silicon with a remarkably clean interface. Germanium’s oxide dissolves in water; GaAs has no comparable stable oxide. $\mathrm{Si}{\mathrm{O}}_2$ plays two roles in fabrication:

• an insulator inside devices (for example the gate dielectric of a MOSFET);
• a barrier (mask) against diffusion of dopants during fabrication (see 4.1.2).

The chemistry. Silicon is highly reactive. Expose a bare wafer to air at room temperature and a native oxide a few nanometres thick forms instantly. To get a controllable, thicker layer, the wafer is heated and exposed to oxygen or water vapour. The key physical point: the oxidizing species (O${}_2$ or H${}_2$O) diffuses through the oxide already present and reacts at the Si-SiO${}_2$ interface, not at the outer surface. So new oxide is made at the bottom, consuming silicon (about 44% of the final oxide thickness is silicon taken from the wafer), and the interface moves into the wafer. (That 44% figure is standard background, not stated in this text.)

The two overall reactions are

$\mathrm{Si}+{\mathrm{O}}_2\to \mathrm{Si}{\mathrm{O}}_2\text{(4.1a, dry oxidation)}$

$\mathrm{Si}+2{\mathrm{H}}_2\mathrm{O}\to \mathrm{Si}{\mathrm{O}}_2+2{\mathrm{H}}_2\text{(4.1b, wet oxidation)}$

	Dry oxidation	Wet oxidation
Oxidant	${\mathrm{O}}_2$ gas	water vapour
Growth rate	slower	faster
Interface quality	superior Si-SiO${}_2$ interface	poorer
Typical use	most critical insulators, e.g. MOSFET gate oxide	thick barrier / field oxides

Thought experiment. Water is far more soluble in the growing oxide, so many more oxidant molecules get through the glass per second than with ${\mathrm{O}}_2$. That is the intuition for “wet is fast”. Dry is slow but gentle, like carefully laying a brick floor versus pouring concrete quickly.

The furnace (Figs. 4.1 and 4.2). The wafers (typically many at once) stand on a slotted quartz boat that is pushed by an insertion rod into a long, clear fused-quartz tube inside a resistance-heated furnace. Features:

• Operating temperature $800{}^{\circ }\mathrm{C}$ to $1200{}^{\circ }\mathrm{C}$.
• Heater coils in three separately controlled zones: the two outer zones run at higher power to compensate for heat leaking out of the tube ends, leaving a long centre zone at uniform temperature (controllable to about $\pm 1{}^{\circ }\mathrm{C}$).
• Tube material: usually fused quartz (SiC and polycrystalline Si tubes also used in some cases; the OCR is damaged here).
• Dry oxidation: ${\mathrm{O}}_2$ is simply fed into the back of the tube.
• Wet oxidation: either bubble a carrier gas (Ar or N${}_2$) through heated water, or burn ${\mathrm{O}}_2$ and ${\mathrm{H}}_2$ at the tube input (called pyrogenic wet oxidation).
• Time needed depends on furnace temperature, desired thickness, and crystal orientation of the surface (other factors matter under special conditions).
• In commercial systems loading, insertion, temperature ramping and gas control are fully automated.

Figure 4.2(b) (pictorial): a wafer, ${\mathrm{O}}_2$ or ${\mathrm{H}}_2\mathrm{O}$ arrows, $800$-$1200{}^{\circ }\mathrm{C}$, and afterwards the wafer wears a layer of $\approx 0.01$-$1.0\mu \mathrm{m}$ of $\mathrm{Si}{\mathrm{O}}_2$.

Growth curves (Fig. 4.3). Figure 4.3(a) and (b) plot oxide thickness (log scale, $0.01$ to $\sim 10\mu \mathrm{m}$) against oxidation time (log scale, $0.1$ to $100$ hr) for $(100)$ and $(111)$ silicon. Each panel has dry and wet curves at $900,1000,1100,1200{}^{\circ }\mathrm{C}$. What the figures must show, and what to read from them:

• Higher temperature gives thicker oxide at a given time.
• Wet curves lie above dry curves at the same temperature.
• $(111)$ surfaces oxidize somewhat faster than $(100)$ (more atoms per unit area to react with).
• Growth is roughly linear at early times and slows (parabola-like) at long times, because the oxidant must diffuse through an ever-thicker layer.

Optional extra (not in the book): the Deal-Grove picture. The two regimes follow from $x_o^2+A{x}_o=B(t+\tau )$. For short times $x_o\approx (B/A)(t+\tau )$ (reaction limited, linear); for long times $x_o\approx \sqrt{Bt}$ (diffusion limited, parabolic). The figure’s curves are exactly this behaviour on a log-log plot.

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4.1.2 Diffusion

The idea. Solid-state diffusion is the historic and still widely used method of putting dopant atoms into a crystal. Put the wafer in contact with a solid, liquid or gaseous source of the desired impurity. A reaction at the surface keeps a supply of dopant atoms right next to the crystal. At high temperature the atoms slowly wander (diffuse) into regions of the wafer not protected by oxide, driven simply by the fact that concentration is higher outside than inside: the same random-walk “smelling perfume spread across a room” physics as the carrier diffusion in Chapter 3.

Facts (Fig. 4.4):

• Surface concentrations reach very high values (up to about $10^{21}/\mathrm{c}{\mathrm{m}}^3$), so the surface region adopts the $n$- or $p$-type character of the diffusing atoms; the Fig. 4.4 sketch shows a curve of diffused $n$-dopant concentration decaying with depth $x$ and crossing the original uniform $p$-dopant level, which marks the junction depth.
• Dopants also diffuse into $\mathrm{Si}{\mathrm{O}}_2$, but slowly for common dopants, so oxide protects underlying Si only for a limited time. The masking time depends on oxide thickness, diffusion temperature and the background doping.

The equipment. Diffusion is done in an open-tube furnace identical in construction to the oxidation furnace; temperatures are similar ($\approx 900$-$1200{}^{\circ }\mathrm{C}$). The only change is a dopant source in place of the oxidizing ambient.

Example: phosphorus from a liquid source (Fig. 4.5).

1. ${\mathrm{N}}_2$ carrier gas bubbles through liquid phosphorus oxychloride ($\mathrm{POC}{\mathrm{l}}_3$, a liquid at room temperature) and carries its vapour into the tube.
2. A small amount of ${\mathrm{O}}_2$ simultaneously admitted reacts with $\mathrm{POC}{\mathrm{l}}_3$ to deposit ${\mathrm{P}}_2{\mathrm{O}}_5$ on the wafer.
3. Silicon reduces ${\mathrm{P}}_2{\mathrm{O}}_5$, liberating P atoms that diffuse into the Si.

Two-step process. At the higher temperatures undesirable surface compounds tend to form, so the process is split:

Step	Source	Temperature	Purpose
Predeposition	present	moderate	introduce a controlled amount of dopant near the surface
Drive-in	cut off	increased	drive the already-introduced dopant deeper, faster

Mathematics (Eqs. 4.2). Neglecting second-order effects the dopant concentration $N(x,t)$ obeys Fick’s second law (the diffusion equation, same form as the minority-carrier equation of Chapter 3 without R-G):

$\frac{\partial N}{\partial t}=D\frac{{\partial }^{2}N}{\partial x^2}$

Predeposition. The surface is held at fixed concentration $N_0$ (source-limited), and the wafer is initially dopant-free:

$N(0,t)=N_0,N(x\to \infty ,t)=0,N(x,0)=0(x>0).$

The solution is

$N_1(x,t_1)=N_0\mathrm{erfc}\left(\frac{x}{2\sqrt{D_1{t}_1}}\right)\text{(4.2a)}$

Verification (every step). Let $\eta =x/(2\sqrt{Dt})$ and $N=N_0\mathrm{erfc}(\eta )$, with $\frac{d}{d\eta }\mathrm{erfc}\eta =-\frac{2}{\sqrt{\pi }}{e}^{-{\eta }^2}$.

$\frac{\partial \eta }{\partial x}=\frac{1}{2\sqrt{Dt}},\frac{\partial \eta }{\partial t}=-\frac{\eta }{2t}$

$\frac{\partial N}{\partial t}=N_0\left(-\frac{2}{\sqrt{\pi }}{e}^{-{\eta }^2}\right)\left(-\frac{\eta }{2t}\right)=\frac{N_0\eta e^{-{\eta }^2}}{\sqrt{\pi }t}$

$\frac{\partial N}{\partial x}=-\frac{N_0}{\sqrt{\pi Dt}}{e}^{-{\eta }^2}$

$\frac{{\partial }^{2}N}{\partial x^2}=-\frac{N_0}{\sqrt{\pi Dt}}{e}^{-{\eta }^2}(-2\eta )\frac{1}{2\sqrt{Dt}}=\frac{N_0\eta e^{-{\eta }^2}}{\sqrt{\pi }Dt}$

$D\frac{{\partial }^{2}N}{\partial x^2}=\frac{N_0\eta e^{-{\eta }^2}}{\sqrt{\pi }t}=\frac{\partial N}{\partial t}✓$

Also $\mathrm{erfc}(0)=1$ gives $N(0,t)=N_0$ and $\mathrm{erfc}(\infty )=0$. The natural length is the diffusion length $2\sqrt{D_1{t}_1}$: the profile is essentially “one erfc, stretched”.

Dose retained after predeposition.

$Q={\int }_0^{\infty }{N}_{1}dx=N_{0}2\sqrt{D_1{t}_1}{\int }_0^{\infty }\mathrm{erfc}(\eta )d\eta =N_{0}2\sqrt{D_1{t}_1}\frac{1}{\sqrt{\pi }}=\frac{2N_0\sqrt{D_1{t}_1}}{\sqrt{\pi }}$

using ${\int }_0^{\infty }\mathrm{erfc}(\eta )d\eta =1/\sqrt{\pi }$.

Drive-in. The source is removed, so the dopant already in the wafer (dose $Q$) simply spreads, with no dopant crossing the surface: $\partial N/\partial x{|}_{x=0}=0$. The solution is a half-Gaussian whose area stays $Q$:

$N_2(x,t_2)=\frac{Q}{\sqrt{\pi D_2{t}_2}}\exp \left(-\frac{x^2}{4D_2{t}_2}\right)$

Substituting $Q$:

$N_2(x,t_2)=\frac{2}{\pi }{N}_0\sqrt{\frac{D_1{t}_1}{D_2{t}_2}}\exp \left(-\frac{x^2}{4D_2{t}_2}\right)\text{(4.2b, valid when }{D}_2{t}_2\gg D_1{t}_1\text{)}$

The OCR of Eq. 4.2b is truncated; it is printed in the book with a prefactor of the form $N_0\sqrt{D_1{t}_1/D_2{t}_2}$ times the Gaussian, and the inequality $D_2{t}_2\gg D_1{t}_1$ is the condition that the predeposited profile is thin compared with the drive-in spread (so it can be treated as a delta function at the surface). The derivation above shows the exact numerical factor is $2/\pi$. The dependence (everything scales as $\sqrt{D_1{t}_1/D_2{t}_2}{e}^{-x^2/4D_2{t}_2}$) is what matters physically.

Symbols: subscripts 1 and 2 denote predeposition and drive-in; $x$ is depth from the surface; $N_0$ is the surface concentration during predeposition (set by solid solubility); $D$ is the diffusion coefficient for the given impurity and furnace temperature (it rises roughly exponentially with temperature); $t$ is the duration. $\mathrm{erfc}$ is the complementary error function found in math handbooks.

Fig. 4.6 (sample computation). Phosphorus predeposition at $1000{}^{\circ }\mathrm{C}$ for $10$ min, then drive-in at $1200{}^{\circ }\mathrm{C}$ for $30$ min, with $N_0\sim 10^{21}\mathrm{c}{\mathrm{m}}^{-3}$ and $D\approx 2.58\times 10^{-14}\mathrm{c}{\mathrm{m}}^2/s$ for the predeposition (the remaining parameters are cut off in the OCR). The figure is a semilog plot of phosphorus concentration ($10^{15}$ to $10^{21}\mathrm{c}{\mathrm{m}}^{-3}$ roughly) versus $x$ from $0$ to $5\mu \mathrm{m}$ showing two curves: a steep erfc “predeposition” curve that is very shallow (a fraction of a micron), and a much flatter, deeper Gaussian “drive-in” curve with a lower surface concentration. The moral: drive-in trades surface concentration for depth, conserving the total dose.

Worked illustration (mine). Predeposition: $D_1{t}_1=(2.58\times 10^{-14})(600\mathrm{s})=1.55\times 10^{-11}\mathrm{c}{\mathrm{m}}^2$, so $2\sqrt{D_1{t}_1}=2\sqrt{1.55\times 10^{-11}}=7.9\times 10^{-6}\mathrm{cm}=0.079\mu \mathrm{m}.$ Dose (with $N_0=10^{21}$): $Q=2N_0\sqrt{D_1{t}_1/\pi }=2\times 10^{21}\times 2.22\times 10^{-6}\approx 4.4\times 10^{15}\mathrm{c}{\mathrm{m}}^{-2}$. The drive-in then lowers the surface concentration to $N_2(0)=Q/\sqrt{\pi D_2{t}_2}$, and the larger $D_2{t}_2$ is, the lower and deeper the profile.

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4.1.3 Ion Implantation

The idea. Instead of coaxing dopants in with heat, shoot them in. Create ions of the impurity, accelerate them to energies from $5\mathrm{keV}$ to $1\mathrm{MeV}$, and literally fire them into the semiconductor. Picture a microscopic shotgun; the ions slow by collisions and stop at a depth that depends on their energy. Because of the need for shallower junctions, lower-temperature processing and more precise control, implantation has become a workhorse process.

Damage and anneal. Implanted ions knock semiconductor atoms off their lattice sites along the path, and the ions themselves do not necessarily stop on lattice sites (so they are not yet electrically active). A follow-up anneal (heating) is therefore an integral part of the process: it repairs crystal damage and activates the dopants by letting them settle on substitutional sites.

The machine (Figs. 4.7 and 4.8). Left to right in Fig. 4.7:

Component	Job
Ion source	ionizes the desired impurity (also produces unwanted ions)
Analyzer magnet / mass analyzer (with resolving aperture)	bends the beam; only the desired mass/charge passes, removing unwanted ions
Acceleration tube (high-voltage terminal)	accelerates ions to the preset energy
Lens (focus)	focuses the beam
x-scan and y-scan plates	electrostatically sweep the beam over the wafer (or the wafer is moved mechanically, or both)
Wafer (target) and beam mask	the target
Faraday cup	collects charge to measure the beam current

An electrical contact to the wafer lets electrons flow in to neutralize the implanted ions. Integrating the target current over the implant time counts the ions exactly. The total number of implanted ions per unit area is the dose $\Phi$ (ions/cm${}^2$). Fig. 4.8 photographs show the commercial end-station: a wafer carousel in two ports and robot arms that automatically load and unload it.

The profile (Eq. 4.3). The implanted concentration has a Gaussian shape:

$N(x)=\frac{\Phi }{\sqrt{2\pi }\Delta R_p}\exp \left\{-\frac{1}{2}{\left[\frac{x-R_p}{\Delta R_p}\right]}^2\right\}\text{(4.3)}$

For readers who know statistics: $R_p$ is the mean (the projected range) and $\Delta R_p$ the standard deviation (the straggle). Both depend on ion species and substrate, and are roughly proportional to ion energy. Key consequences:

${\int }_{-\infty }^{\infty }Ndx=\Phi (\text{normalized}),N_{\max }=N(R_p)=\frac{\Phi }{\sqrt{2\pi }\Delta R_p}\approx \frac{0.4\Phi }{\Delta R_p}.$

(The integral is $\Phi$ because a Gaussian pdf of unit area times $\Phi$; the small part with $x<0$ is neglected when $R_p\gg \Delta R_p$.) Unlike diffusion, the peak is buried at depth $R_p$ below the surface, not at it.

Fig. 4.9. Computed P implants into Si at constant dose $10^{14}\mathrm{c}{\mathrm{m}}^{-2}$ for energies $25,50,75,100\mathrm{keV}$: semilog curves from $x=0$ to $0.4\mu \mathrm{m}$. Each is a bell (parabola on a log axis) peaking at $R_p$ with a peak concentration near $10^{19}$ to $10^{20}\mathrm{c}{\mathrm{m}}^{-3}$; higher energy means deeper $R_p$, broader curve and lower peak (same area).

Worked illustration (mine; approximate range statistics). A $50$ keV phosphorus implant into Si has $R_p\approx 0.06\mu \mathrm{m}$ and $\Delta R_p\approx 0.024\mu \mathrm{m}$. For $\Phi =10^{14}\mathrm{c}{\mathrm{m}}^{-2}$: $N_{\max }=\frac{10^{14}}{\sqrt{2\pi }(2.4\times 10^{-6}\mathrm{cm})}=\frac{10^{14}}{6.0\times 10^{-6}}\approx 1.7\times 10^{19}\mathrm{c}{\mathrm{m}}^{-3}.$

Masking. As with diffusion, parts of a wafer can be masked: thin films of $\mathrm{Si}{\mathrm{O}}_2$, $\mathrm{S}{\mathrm{i}}_3{\mathrm{N}}_4$, and less frequently photoresist and Al stop the ions before they reach the silicon.

Advantages over diffusion.

1. Intrinsically low temperature (implant itself at room temperature). The anneal is often some other high-temperature step already in the flow (such as a later oxidation); a dedicated anneal can be as low as $600{}^{\circ }\mathrm{C}$ under optimum conditions.
2. Minimal spreading of the profile.
3. Very precise control of the impurity amount (dose from current integration).
4. Virtually any atom into any substrate. A striking recent use: implanting high doses of oxygen to produce a buried $\mathrm{Si}{\mathrm{O}}_2$ layer, giving silicon-on-insulator (SOI) structures.
5. Shallow profiles (Fig. 4.9). Implants have therefore replaced the predeposition step of diffusion and are ideal for devices needing extremely shallow junctions.

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4.1.4 Lithography

Purpose. Masks of $\mathrm{Si}{\mathrm{O}}_2$ and other materials must have openings in exactly the right places; metals must be patterned into wires. Lithography (literally “stone writing”) selectively removes a thin film at prescribed positions across the wafer surface. It is the printing press of chip making. Fig. 4.10 shows a production line: a coat-and-develop system (the SSI150) next to a Nikon stepper, with wafers moving between them automatically on tracks.

The steps (Fig. 4.11), using patterning of an $\mathrm{Si}{\mathrm{O}}_2$ film as the example.

1. Resist coating. Coat the oxide-covered wafer with photoresist, a UV-sensitive liquid. A few drops are placed on the wafer, which is spun at high speed to make a thin uniform coat.
2. Prebake at $80$-$100{}^{\circ }\mathrm{C}$ to drive out solvent and improve adhesion. The hardened resist resembles a photographic emulsion.
3. Exposure through a mask with UV light (Fig. 4.11b). The mask is a carefully made glass or quartz photoplate carrying a copy of the pattern; darkened emulsion regions block UV. Exposed resist changes chemically, in a way depending on the resist type:

	Negative resist	Positive resist
Effect of light	exposed areas polymerize, harder to remove	sensitizer breaks down, exposed regions dissolve faster
After developer	exposed regions remain, unexposed wash away	exposed regions are removed, unexposed remain
Remark	widely used in early IC processing	now the main type: better small-geometry control

For a positive resist the sensitizer (present in large amounts) dramatically slows dissolution in an alkaline developer until light destroys it. Fig. 4.11(c): left half (positive) has a window where the mask was clear; right half (negative) has resist where the mask was clear.

4. Develop (Fig. 4.11c).
5. Hard bake, $30$ min at $120$-$180{}^{\circ }\mathrm{C}$: improves adhesion and resistance to the etch.
6. Etch the unprotected oxide with an acid, buffered HF for $\mathrm{Si}{\mathrm{O}}_2$ (Fig. 4.11d).
7. Strip the resist, either with a chemical solution that swells and lifts it, or by oxidizing (burning) it in an oxygen plasma system called an asher.

Limits. Ever-shrinking features push UV lithography: shorter-wavelength sources and special compensating techniques extended the minimum feature size, and x-ray lithography was under development and expected soon.

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4.1.5 Thin-Film Deposition

Devices must be wired to the outside world: metal layers must be deposited and patterned. Complex ICs have three, sometimes four, electrically isolated metal layers, which needs intervening dielectric layers. Thin films also act as interdiffusion barriers and protect circuits from contamination.

Evaporation

An old, direct method. Place the source (for Al, a short piece of wire on a tungsten filament or boat) on a resistance-heated holder inside a vacuum chamber (Fig. 4.12) with the substrate facing it. Pump down, heat the source, and vapour travels unimpeded (low pressure means few collisions) to condense as a thin film on the wafer.

• Hot-filament evaporation: moderately high contamination (filament material).
• Electron-beam evaporation (source heated by e-beam): no contamination, but it generates x-rays that degrade devices.
• Therefore seldom used in production-line modern ICs, but still common for simple devices.

Sputtering

Also in vacuum, but the source (“target”) sits on the cathode of a parallel-plate system and the wafer on the anode (Fig. 4.13).

1. Evacuate, then admit low-pressure argon.
2. Apply an interelectrode voltage; Ar ionizes, forming a plasma.
3. The source plate is negative, so $\mathrm{A}{\mathrm{r}}^{+}$ ions accelerate into it.
4. The impacts knock out source atoms/molecules (momentum transfer, like a cue ball breaking a rack).
5. Being neutral, they travel to the substrate and form the film.

A d.c. supply suffices for metals; RF is needed for insulating films (otherwise charge builds up on the insulator). For compounds, a gas containing one component may be added to keep the film near stoichiometric. Low-temperature, low-contamination, acceptable throughput: sputtering is the chief commercial method for Al and other metals.

Chemical Vapor Deposition (CVD)

The film forms from gas-phase components: a compound decomposes, or gases react. The reactions are almost always surface catalyzed, so film grows on the wafer surfaces placed in the gas stream.

Type	Features
APCVD (atmospheric pressure)	simple systems
LPCVD (low pressure)	comparable kinetics, better uniformity, less gas consumption
PECVD (plasma-enhanced)	plasma electrons energize reaction gases, allowing very low deposition temperatures

Fig. 4.14 is a cutaway barrel reactor: wafers stand on a central susceptor heated radiantly by surrounding quartz lamps (infrared sensors monitor temperature), process gases enter at the top, flow across the wafers and exit coaxially at the bottom. CVD makes the masking and inter-metal dielectric films of complex ICs, and polycrystalline Si (a pseudo-metal when heavily doped). All three CVD types appear somewhere in a typical IC flow.

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4.1.6 Epitaxy

Evaporation, sputtering and CVD give amorphous or polycrystalline films. Epitaxy (Greek epi “upon” + taxis “arrangement”) yields a single-crystal layer that is an extension of the substrate lattice: new atoms obey the pattern of the crystal beneath, like children’s blocks added neatly to an existing perfect stack.

For silicon: vapour-phase decomposition of $\mathrm{SiC}{\mathrm{l}}_4$ or silanes ($\mathrm{Si}{\mathrm{H}}_4,\mathrm{Si}{\mathrm{H}}_2\mathrm{C}{\mathrm{l}}_2,\mathrm{SiHC}{\mathrm{l}}_3$) in a reactor like the CVD one (Fig. 4.14) lets Si literally grow on the existing crystal. The epi-layer doping, intentionally different from the substrate’s, is set by adding a dopant gas: phosphine ($\mathrm{P}{\mathrm{H}}_3$), diborane (${\mathrm{B}}_2{\mathrm{H}}_6$) or arsine ($\mathrm{As}{\mathrm{H}}_3$). Whole-wafer epitaxy must be done early in the flow, before any permanent surface films are grown or deposited. Wafers are sometimes purchased with the epi-layer already in place.

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4.2 Device Fabrication Examples

The purpose: to show how individual processes are combined and sequenced. Two examples, both qualitative.

4.2.1 $pn$ Junction Diode Fabrication

Starting point: a flat, damage-free, single-crystal Si wafer, precleaned to remove particulates, organic films and adsorbed metal ions. Here it is $p$-type, uniformly boron-doped during crystal growth. Fig. 4.15 steps:

Step	Process	What happens
(0)	Start	$p$-Si wafer
(1)	Oxidation	grow thermal $\mathrm{Si}{\mathrm{O}}_2$, a diffusion barrier. Its thickness must be comfortably greater than the projected masking thickness
(2)	**Lithography 1 (positive resist assumed)	open “diffusion holes” in the oxide where the diodes will be
(3)	Phosphorus diffusion (predeposition then drive furnaces)	forms $n^{+}$-$p$ junctions where oxide does not protect the surface. The ”+” in $n^{+}$ means very heavy doping
(4)	Metallization	sputter (or evaporate) Al over the entire wafer
(5)	**Lithography 2	remove excess metal outside the junction areas

Practical notes: some oxygen is needed in the P predeposition (as in 4.1.2); the drive-in may be in an oxidizing atmosphere to minimize out-diffusion, so after diffusion a subsidiary lithography step is usually needed to reopen the oxide holes (not shown in Fig. 4.15). A low-temperature anneal ($\le 500{}^{\circ }\mathrm{C}$) promotes a low-resistance metal-Si contact.

Diodes now work across the wafer. For commercial parts a diamond-edged saw cuts the wafer into dice (a die is a wafer piece with a single device or IC); a large-area metal contact is made on the die back, a lead attached to the top contact, and the device encapsulated in plastic or hermetically sealed in a metal package.

4.2.2 Computer CPU Process Flow

This is a direct excerpt (with permission) of Intel’s Components Quality and Reliability 1991/92. Fig. 4.16 is the block diagram of the single poly, single metal, CHMOS flow. The blocks, in order, include: starting silicon wafer; initial oxidation; well ion implant plus drive; silicon-nitride deposition and patterning; field threshold ion implant; field oxidation; silicon-nitride removal; gate oxidation; transistor threshold ion implant; polycide deposition plus impurity doping; polycide patterning plus oxidation; n-channel source-drain implant; p-channel source-drain implant; poly re-ox; doped glass deposition; contact etch; metal deposition; metal patterning; passivation; alloy; wafer backside preparation; process control/electrical test; wafer sort; assembly; class test; outgoing quality monitor; customer. (Between most blocks are lithography “MASK” steps.)

Vocabulary.

• Poly: polycrystalline Si.
• CHMOS: Complementary High-density Metal-Oxide-Semiconductor, a fabrication technology placing both $n$-channel and $p$-channel MOS transistors on one chip. “Single poly, single metal” means one level of heavily doped polysilicon and one level of metal contact and interconnect the devices.
• Wet etch: dissolving a material (such as $\mathrm{Si}{\mathrm{O}}_2$) in a liquid chemical bath.
• Dry etch: removing material by a plasma-enhanced gas-phase reaction.

The author asks that the description be “looked over, not digested”. Here are the 11 stages (Fig. 4.17 a-l), with a one-line meaning.

1. Starting silicon and well definition (4.17a). $150$ mm (6 in.) high-resistivity $(100)$ boron-doped $p$-type wafers. $p$-type is needed for $n$-channel transistors. For $p$-channel transistors, $n$-type regions ($n$-wells) are implanted (As or P) through a mask. The $n$-well is the background for $p$-channel devices; the protected $p$-type substrate is the background for $n$-channel ones. A high-temperature drive finishes the wells. Analogy: neighbouring plots of land, one planted for rice and one for wheat, on the same field.
2. Field threshold implant and field oxidation (4.17b,c). Silicon nitride ($\mathrm{S}{\mathrm{i}}_3{\mathrm{N}}_4$) is deposited, masked and etched. Etched-away nitride defines where the field threshold implant goes and where oxide may grow in field oxidation; remaining nitride blocks oxide growth (these are future transistor sites). The thick (about $6000\text{A˚}$) field oxide electrically isolates adjacent transistors. Nitride is then removed.
3. Gate oxidation (4.17d). Grow a thin, dense thermal oxide everywhere; what remains after processing is the MOS gate oxide. Performance depends critically on its quality (hence dry oxidation).
4. Transistor threshold implant (4.17d). A boron implant adjusts the threshold voltage $V_T$ of both device types. Thick field oxide keeps the boron out of isolation regions.
5. Polysilicon-to-diffusion (buried) contacts (4.17e). Openings are defined in the thin gate oxide where poly must contact diffused silicon regions.
6. Polycide deposition, doping, patterning, oxidation (4.17f,g). About $1500\text{A˚}$ of poly deposited by CVD, doped with phosphorus by gas-source diffusion (which also diffuses through poly into the substrate, lowering buried-contact resistance). About $1500\text{A˚}$ of silicide deposited conformally on top to lower resistance and increase speed in small transistors. The polycide stack (poly + silicide) is defined by plasma dry etch using resist as mask, then oxidized to protect the gates.
7. Source and drain implants and poly re-ox (4.17h). The polycide gate stack, thin oxide, field oxide and resist form the mask for the $p$-channel and $n$-channel source/drain implants. This is the self-aligned source/drain process: the source and drain are aligned directly to the gate, which fixes their location relative to the channel. (Intuition: the gate is its own stencil, so the alignment cannot be wrong, regardless of mask-alignment errors.) After removing remaining poly oxide, a re-ox high-temperature oxidation (a) drives in the S/D implants, (b) grows a high-integrity dielectric on poly, (c) caps exposed S/D regions to prevent out-diffusion during later glass deposition.
8. Doped glass deposition (4.17i). $5000$-$10,000\text{A˚}$ of boron- and/or phosphorus-doped silicate glass (BPSG) deposited by low-temperature CVD for electrical isolation between the metal lines and the underlying gates and devices; then prepared for masking.
9. Contact mask and etch (4.17j). Open windows for metal-to-polycide and metal-to-silicon contact holes, by wet, dry or wet+dry etch. In a wet/dry combination the wet etch gives a sloped top for better metal step coverage, and an isotropic dry etch removes the remaining glass leaving vertical sidewalls.
10. Metal deposition and definition (4.17k). Sputter metal; pattern it. These lines connect transistors to the outside world and apply the voltages that turn transistors on and off.
11. Passivation (4.17l). PECVD deposits a dual film: oxynitride (moisture and contamination barrier, vital for plastic packages since plastic is a poor moisture barrier) under plasma oxide (handling protection).

The remaining flow steps (Fig. 4.16, right column) prepare for die separation and packaging. Fig. 4.18 is a photograph of an Intel Pentium processor die about $1.5$ cm square containing $3.1$ million transistors, with labelled functional units: instruction fetch, branch prediction, code cache, instruction decode, code TLB, clock driver, bus interface, superscalar integer execution units, pipelined floating-point unit, data TLB, and data cache. (Fabricated by an upgraded version of the described process.)

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4.3 Summary

The tour of silicon device fabrication gave a feel for the construction and physical nature of devices:

• Component processes: oxidation, diffusion, ion implantation, lithography, evaporation, sputtering, chemical vapor deposition and epitaxy.
• Sequencing: a simple $pn$ diode (oxidize, open windows, diffuse, metallize, pattern) and a moderately complex IC (CHMOS) show how the same processes are combined, again and again, to build real structures.

Key formulas of the chapter

Quantity	Formula
Wet / dry oxidation	$\mathrm{Si}+2{\mathrm{H}}_2\mathrm{O}\to \mathrm{Si}{\mathrm{O}}_2+2{\mathrm{H}}_2$ ; $\mathrm{Si}+{\mathrm{O}}_2\to \mathrm{Si}{\mathrm{O}}_2$
Predeposition profile	$N_1=N_0\mathrm{erfc}(x/2\sqrt{D_1{t}_1})$
Drive-in profile	Gaussian $\propto \exp (-x^2/4D_2{t}_2)$, with $D_2{t}_2\gg D_1{t}_1$
Implant profile	$N=\frac{\Phi }{\sqrt{2\pi }\Delta R_p}\exp \{-\frac{1}{2}[(x-R_p)/\Delta R_p{]}^2\}$

End-of-chapter problems / computer exercises: none (read-only chapter).

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Part I Supplement and Review

Part I covered Chapters 1-3 (crystals, bands, carriers, transport, recombination-generation) plus the read-only Chapter 4. This supplement collects the reading list, figure sources, a self-test vocabulary list and two review problem sets with answer keys. Chapter 4 itself is not examined in the problem sets.

R1.1 Alternative / Supplemental Reading List

Author(s)	Type (A = alternative, S = supplemental)	Level	Relevant chapters
For semiconductor physics
Ferendeci	A/S	Advanced undergrad / intro grad	1-6
Neamen	A	Undergraduate	1-6
Pierret	S	Introductory graduate	1-6
Streetman	A	Undergraduate	1-4
Tyagi	A/S	Advanced undergrad / intro grad	1-5
For device fabrication
Jaeger	S	Undergraduate	All
Runyan and Bean	S	Professional	All
Sze (editor)	S	Professional	All

Full citations:

1. A. M. Ferendeci, Physical Foundations of Solid State and Electron Devices, McGraw-Hill, 1991.
2. R. C. Jaeger, Introduction to Microelectronic Fabrication, Vol. V, Modular Series on Solid State Devices (Neudeck and Pierret, eds.), Addison-Wesley, 1988.
3. D. A. Neamen, Semiconductor Physics and Devices, Basic Principles, Irwin, 1992.
4. R. F. Pierret, Advanced Semiconductor Fundamentals, Vol. VI, Modular Series, Addison-Wesley, 1987.
5. W. R. Runyan and K. E. Bean, Semiconductor Integrated Circuit Processing Technology, Addison-Wesley, 1990.
6. B. G. Streetman, Solid State Electronic Devices, 4th ed., Prentice Hall, 1995.
7. S. M. Sze (ed.), VLSI Technology, 2nd ed., McGraw-Hill, 1988.
8. M. S. Tyagi, Introduction to Semiconductor Materials and Devices, Wiley, 1991.

Other recent texts: Bar-Lev (Prentice Hall, 1993); Navon (Holt, Rinehart and Winston, 1986); Pulfrey and Tarr (Prentice Hall, 1989); Sah (World Scientific, 1991); Singh (McGraw-Hill); Sze, Semiconductor Devices: Physics and Technology (Wiley, 1985); Yang, Microelectronic Devices (McGraw-Hill); Zambuto, Semiconductor Devices (McGraw-Hill, 1989). (Years partly garbled in OCR.)

R1.2 Figure Sources / Cited References

(1) Shockley, Electrons and Holes in Semiconductors (1950); (2) Sze, Physics of Semiconductor Devices, 2nd ed. (Wiley, 1981); (3) a Springer-Verlag reference (1982, title lost in OCR); (4) Jacoboni, Canali, Ottaviani, Quaranta, “A Review of Some Charge Transport Properties of Silicon,” Solid-State Electronics 20, 77 (1977); (5) Smith, Frey, Chatterjee, “High-Field Transport of Holes in Silicon,” Appl. Phys. Lett. 39, 332 (1981); (6) Schroder, Semiconductor Material and Device Characterization (Wiley, 1990); (7) Pierret, Advanced Semiconductor Fundamentals; (8) Jaeger, Introduction to Microelectronic Fabrication; (9) Runyan and Bean; (10) T. Deacon, “Silicon Epitaxy: An Overview,” Microelectronic Manufacturing and Testing, Sept. 1984.

R1.3 Review List of Terms

The book asks you to define these in your own words. Here are compact definitions to check yourself against.

#	Term	Meaning
1	amorphous	no long-range atomic order
2	polycrystalline	many small single-crystal grains with random orientations
3	crystalline	atoms in a periodic array throughout
4	lattice	the periodic set of points on which the atom pattern repeats
5	unit cell	smallest volume that, translated, fills space and reproduces the crystal
6	ingot	large single-crystal boule pulled from the melt, sliced into wafers
7	carrier	mobile charge: electron or hole
8	electron	negative carrier in the conduction band
9	hole	missing valence electron; behaves as a positive carrier
10	conduction band	lowest band of allowed states that is empty at 0 K
11	valence band	highest band filled at 0 K
12	band gap	$E_G=E_C-E_V$, the forbidden energy range
13	effective mass	$m^{\ast }$ absorbing lattice forces so $F=m^{\ast }a$
14	intrinsic semiconductor	pure; $n=p=n_i$
15	extrinsic semiconductor	doped so one carrier type dominates
16	dopant	deliberately added impurity
17	donor	impurity giving an electron to the conduction band
18	acceptor	impurity capturing a valence electron, creating a hole
19	n-type	electrons are majority
20	p-type	holes are majority
21	$n^{+}$ ($p^{+}$)	very heavily doped
22	majority carrier	the more abundant carrier
23	minority carrier	the less abundant carrier
24	density of states	number of allowed states per unit energy per unit volume, $g(E)$
25	Fermi function	$f(E)=1/[1+e^{(E-E_F)/kT}]$, occupation probability
26	Fermi energy (level)	energy where $f=1/2$
27	nondegenerate	$E_F$ more than a few $kT$ inside the gap; Boltzmann statistics hold
28	degenerate	$E_F$ within about $3kT$ of, or inside, a band
29	charge neutrality	$p-n+N_D^{+}-N_A^{-}=0$ in a uniformly doped sample
30	extrinsic temperature region	$n\approx N_D$ (or $p\approx N_A$), all dopants ionized
31	intrinsic temperature region	$n_i\gg$ doping, so $n\approx p\approx n_i$
32	freeze-out	at very low $T$ carriers fall back onto donors/acceptors
33	drift	carrier motion caused by an electric field
34	scattering	collisions that randomize carrier velocity
35	thermal motion	random motion with $\frac{1}{2}{m}^{\ast }{v}_{th}^2\sim \frac{3}{2}kT$
36	drift velocity	average velocity from an applied field
37	saturation velocity	limiting drift velocity at high field ($\sim 10^7$ cm/s in Si)
38	current density	charge crossing unit area per unit time
39	mobility	$\mu =v_d/\mathcal{E}$
40	resistivity	$\rho =1/\sigma$
41	conductivity	$\sigma =q({\mu }_{n}n+{\mu }_{p}p)$
42	band bending	position-dependent band edges caused by an electrostatic potential
43	diffusion	net flow from high to low concentration
44	diffusion coefficient	$D$ in $J=qDdn/dx$; $D=(kT/q)\mu$
45	recombination	an electron-hole pair annihilates
46	generation	an electron-hole pair is created
47	band-to-band R-G	direct electron transition across the gap
48	R-G centers	deep-level traps giving two-step R-G
49	E-k plots	energy vs wavevector band diagrams
50	direct semiconductor	conduction minimum and valence maximum at the same $k$ (GaAs)
51	indirect semiconductor	extrema at different $k$ (Si, Ge)
52	photogeneration	pair creation by absorbed photons ($h\nu \ge E_G$)
53	absorption coefficient	$\alpha$; light intensity decays as $e^{-\alpha x}$
54	low-level injection	excess minority carriers $\ll$ majority concentration
55	equilibrium	no external perturbation; $np=n_i^2$, constant $E_F$
56	perturbation	any external influence driving the system from equilibrium
57	steady state	time-independent, but not necessarily equilibrium
58	minority carrier lifetime	$\tau$, mean time before recombination
59	minority carrier diffusion length	$L=\sqrt{D\tau }$
60	quasi-Fermi level	$F_N$, $F_P$ describing non-equilibrium carrier populations
61	dry oxidation	oxidizing Si with ${\mathrm{O}}_2$
62	wet oxidation	oxidizing Si with water vapour
63	predeposition	first diffusion step introducing dopant at fixed surface concentration
64	drive-in	second step redistributing dopant deeper, source off
65	diffusion mask	film (usually $\mathrm{Si}{\mathrm{O}}_2$) blocking dopant diffusion
66	ion implantation	shooting accelerated dopant ions into the wafer
67	dose	implanted ions per cm${}^2$, $\Phi$
68	projected range	mean implant depth $R_p$
69	photoresist	light-sensitive coating used to pattern films
70	negative resist	exposed regions remain after development
71	positive resist	exposed regions are removed
72	sputtering	ion bombardment ejects target atoms that coat the wafer
73	CVD	film grown from gas-phase reactions
74	LPCVD	CVD at low pressure
75	PECVD	plasma-enhanced CVD
76	epitaxy	single-crystal layer extending the substrate lattice
77	die	wafer piece holding one device or IC
78	poly	polycrystalline silicon
79	wet etch	etching in a liquid chemical bath
80	dry etch	plasma/gas-phase etching

R1.4 Part I Review Problem Sets and Answers

Problem Set A was adapted from a one-hour open-book exam; Set B from a one-hour closed-book exam. Use $T=300$ K, $n_i=10^{10}\mathrm{c}{\mathrm{m}}^{-3}$, $kT=0.0259$ eV.

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Problem Set A (open book; use accurate values)

Problem A1: Crystal geometry

Problem. For the Si diamond unit cell (figure: a cube with the origin at the lower back corner; points A, B, C are on the three axes, at distance $a$ from the origin; point D is on the front face):

(a) Miller indices of the plane through A, B, C. (b) Miller indices of the direction from the origin to D. (c) Nearest-neighbour distance in terms of $a$. (d) How to visualize a donor in the cell.

(The OCR lost the figure. Consistent with the book’s answers: A, B, C are the corners at $(a,0,0)$, $(0,a,0)$, $(0,0,a)$, and D is the face-centre atom at $(a,a/2,a/2)$.)

Solution.

(a) Miller procedure:

$\text{intercepts}=(1,1,1)(\text{in units of }a)$ $\text{reciprocals}=(1,1,1)$ $\text{no fractions to clear}\Rightarrow (111).$

(b) Direction components from the origin to D, in units of $a/2$:

$(a,a/2,a/2)=\frac{a}{2}(2,1,1)\Rightarrow [211].$

(c) In the diamond lattice each atom sits at a quarter of the body diagonal from its nearest neighbour. Body diagonal $=\sqrt{3}a$, so

$d_{nn}=\frac{\sqrt{3}}{4}a.$

(d) A donor is a group-V atom (five valence electrons) replacing one Si atom. Four electrons complete the four bonds; the fifth is a weakly bound extra electron (draw an extra bond or electron on that atom), easily freed into the conduction band.

Problem A2: n-type wafer table

Problem. A Si wafer is uniformly doped $N_D=10^{17}\mathrm{c}{\mathrm{m}}^{-3}$ under equilibrium at 300 K, with ${\tau }_p=10^{-6}$ s. Complete the table of $E_G$, $n_i$, $n_0$, $p_0$, $E_F-E_i$, charge density, ${\mu }_n$, $\rho$, $L_p$, $D_p$.

Solution.

Parameter	Value	Reasoning
$E_G$	1.12 eV	Si band gap at 300 K
$n_i$	$10^{10}\mathrm{c}{\mathrm{m}}^{-3}$	given
$n_0$	$10^{17}\mathrm{c}{\mathrm{m}}^{-3}$	$n_0=N_D$ since $N_D\gg n_i$
$p_0$	$10^3\mathrm{c}{\mathrm{m}}^{-3}$	see below
$E_F-E_i$	0.417 eV	see below
charge density	0	charge neutrality holds in a uniform equilibrium sample
${\mu }_n$	801 cm${}^2$/V s	from Fig. 3.5 at $10^{17}$
$\rho$	0.078 $\Omega$ cm	see below
$L_p$	$2.93\times 10^{-3}$ cm	see below
$D_p$	8.57 cm${}^2$/s	see below

$p_0=\frac{n_i^2}{n_0}=\frac{10^{20}}{10^{17}}=10^3\mathrm{c}{\mathrm{m}}^{-3}$

$E_F-E_i=kT\ln \frac{n_0}{n_i}=0.0259\ln (10^7)=0.0259\times 16.12=0.417\mathrm{eV}$

$\rho =\frac{1}{q{\mu }_n{N}_D}=\frac{1}{(1.6\times 10^{-19})(801)(10^{17})}=\frac{1}{12.8}=0.078\Omega \mathrm{cm}$

(holes are negligible in $\sigma$.) Minority-hole diffusion coefficient from the Einstein relation, with ${\mu }_p\approx 331$ cm${}^2$/V s at this doping (Fig. 3.5):

$D_p=\frac{kT}{q}{\mu }_p=0.0259\times 331=8.57\mathrm{c}{\mathrm{m}}^2/s$

$L_p=\sqrt{D_p{\tau }_p}=\sqrt{(8.57)(10^{-6})}=2.93\times 10^{-3}\mathrm{cm}$

Problem A3: Band diagrams

Problem. (a) On a band diagram, show the usual positions of $E_i$, $E_D$, $E_A$, $E_T$ (trap/R-G centre) and $E_F$ for degenerately doped $p$-type. (b) A Si device in equilibrium at 300 K has the electric-field profile shown (zero for $0\le x\le x_a$, constant negative for $x_a\le x\le x_b$, zero for $x_b\le x\le x_c$), with $N_A=10^{16}\mathrm{c}{\mathrm{m}}^{-3}$ on the left and $N_D=10^{16}\mathrm{c}{\mathrm{m}}^{-3}$ on the right (junction inside the field region). Draw the bands with $E_C$, $E_i$, $E_V$ and $E_F$ and justify. (c) Find $V(x_c)-V(0)$.

Solution.

(a) $E_i$ lies near midgap; $E_D$ lies just below $E_C$; $E_A$ just above $E_V$; $E_T$ lies near midgap (deep level, most effective R-G centre); $E_F$ for degenerate $p$-type lies below $E_V+3kT$, i.e. inside the valence band or within a few $kT$ of its edge. Comment: $E_T$ is a localized level, drawn as a dashed line, not a band.

(b) In equilibrium $E_F$ is position independent. Since

$\mathcal{E}=\frac{1}{q}\frac{d{E}_C}{dx}=\frac{1}{q}\frac{d{E}_i}{dx}=\frac{1}{q}\frac{d{E}_V}{dx},$

zero field means flat bands for $0\le x\le x_a$ and $x_b\le x\le x_c$; a constant negative field means all bands have a constant negative slope in $x_a\le x\le x_b$.

Far from the junction:

$E_i-E_F=kT\ln \frac{N_A}{n_i}=0.0259\ln \frac{10^{16}}{10^{10}}=0.0259(13.82)=0.358\mathrm{eV}(0\le x\le x_a)$

$E_F-E_i=kT\ln \frac{N_D}{n_i}=0.358\mathrm{eV}(x_b\le x\le x_c)$

So the diagram: horizontal $E_F$; on the left $E_i$ is 0.358 eV above $E_F$; the bands slope down linearly across $x_a$-$x_b$; on the right $E_i$ is 0.358 eV below $E_F$. $E_C$ and $E_V$ stay $E_G/2$ above and below $E_i$ everywhere.

(c) Total band drop:

$\Delta E=0.358+0.358=0.716\mathrm{eV}$

Electron energy is $E=-qV$ (plus constant), so

$V(x_c)-V(0)=-\frac{1}{q}\left[E_i(x_c)-E_i(0)\right]=-\frac{-0.716\mathrm{eV}}{q}=+0.716\mathrm{V}.$

Problem A4: Two light flashes

Problem. An $N_D=10^{15}\mathrm{c}{\mathrm{m}}^{-3}$ Si sample at room temperature receives two flashes of light. Each creates $\Delta p_f=10^{10}\mathrm{c}{\mathrm{m}}^{-3}$ holes uniformly. The first is at $t=0$, the second at $t=t_f$, with $t_f$ comparable to ${\tau }_p$; flashes are infinitely short. (a) Sketch $\Delta p(t)$. (b) Is low-level injection valid? (c) Solve for $\Delta p(t)$, $t\ge 0$. (d) Fractional conductivity change right after the first flash, symbolically and numerically (use ${\mu }_n=1350$, ${\mu }_p=458$ cm${}^2$/V s at this doping; the numbers are recovered from the printed answer).

Solution.

(a) $\Delta p$ jumps to $\Delta p_f$ at $t=0$, decays exponentially with time constant ${\tau }_p$ to $\Delta p_f{e}^{-t_f/{\tau }_p}$ at $t_f^{-}$, jumps up by another $\Delta p_f$ to $\Delta p_f(1+e^{-t_f/{\tau }_p})$ at $t_f^{+}$ (below $2\Delta p_f$), then decays exponentially again toward zero.

(b) Maximum excess is below $2\Delta p_f$:

$\Delta p_{max}<2\Delta p_f=2\times 10^{10}\ll n_0=N_D=10^{15}\mathrm{c}{\mathrm{m}}^{-3}$

So yes, low-level injection holds at all times.

(c) For a uniform sample with no field, no gradient and no generation after the flash, the minority-carrier diffusion equation reduces to

$\frac{d\Delta p}{dt}+\frac{\Delta p}{{\tau }_p}=0.$

For $0\le t\le t_f$: general solution $\Delta p=A{e}^{-t/{\tau }_p}$; condition $\Delta p(0)=\Delta p_f\Rightarrow A=\Delta p_f$:

$\Delta p(t)=\Delta p_f{e}^{-t/{\tau }_p}.$

For $t\ge t_f$: general solution $\Delta p=A{e}^{-(t-t_f)/{\tau }_p}$; boundary condition (jump by $\Delta p_f$ at $t_f$):

$\Delta p(t_f^{+})=\Delta p(t_f^{-})+\Delta p_f=\Delta p_f\left(1+e^{-t_f/{\tau }_p}\right)\Rightarrow A=\Delta p_f\left(1+e^{-t_f/{\tau }_p}\right)$

$\Delta p(t)=\Delta p_f\left(1+e^{-t_f/{\tau }_p}\right)e^{-(t-t_f)/{\tau }_p}.$

(d) $\sigma =q({\mu }_{n}n+{\mu }_{p}p)$.

$\sigma (0^{-})=q{\mu }_n{N}_D(n_0=N_D\gg p_0)$

$\sigma (0^{+})=q\left[{\mu }_n(N_D+\Delta p_f)+{\mu }_p(p_0+\Delta p_f)\right]\approx q{\mu }_n{N}_D+q({\mu }_n+{\mu }_p)\Delta p_f$

$\Delta \sigma =q({\mu }_n+{\mu }_p)\Delta p_f$

$\frac{\sigma (0^{+})-\sigma (0^{-})}{\sigma (0^{-})}=\frac{q({\mu }_n+{\mu }_p)\Delta p_f}{q{\mu }_n{N}_D}=\left(1+\frac{{\mu }_p}{{\mu }_n}\right)\frac{\Delta p_f}{N_D}$

$=\left(1+\frac{458}{1350}\right)\frac{10^{10}}{10^{15}}=1.34\times 10^{-5}.$

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Problem Set B (closed book)

Use $n_i=10^{10}$ cm${}^{-3}$, $kT=0.0259$ eV.

I. General information

(1) A cubic cell has one atom centred on each vertical edge and one in the middle of the top and bottom faces. Atoms in the cell? Options: (a) 4, (b) 2, (c) 1, (d) 1/2.

Edge atoms are shared by four cells; face atoms by two:

$N=4\times \frac{1}{4}+2\times \frac{1}{2}=1+1=2.$

Answer: (b).

(2) Lattice name? Options: simple cubic, bcc, fcc, diamond.

Shift the origin to one edge atom: the other atoms are then at the corners and centres of cells of a displaced cube, i.e. every point is a corner or body centre of a cubic cell. One atom at each corner and one at the centre is bcc. Answer: (b).

(3) Miller indices of the plane with intercepts $x=a$, $y=-2a$, $z=3a$.

$\text{intercepts}=1,-2,3$ $\text{reciprocals}=1,-\frac{1}{2},\frac{1}{3}$ $\times 6(\text{lowest common denominator})\Rightarrow 6,-3,2$

So $(6\bar{3}2)$. Answer: (e).

(4) Which direction is not perpendicular to $[100]$? Options: $[0\bar{1}1]$, $[032]$, $[001]$, $[\bar{1}00]$.

Perpendicular means dot product zero; $[100]\cdot [uvw]=u$. Only $[\bar{1}00]$ has nonzero first index ($-1$). Answer: (d).

(5) The occupation probability at $E_C+kT$ is $e^{-10}$. Find $E_F$.

$\frac{1}{1+e^{(E_C+kT-E_F)/kT}}=e^{-10}$ $e^{(E_C+kT-E_F)/kT}=e^{10}-1\approx e^{10}$ $E_C+kT-E_F\approx 10kT$ $E_C-E_F\approx 9kT.$

Answer: (b).

(6) Dominant scattering in lightly doped Si at room temperature: (b) lattice scattering (phonons); impurity scattering matters only at high doping or low $T$.

(7) $D_N$ versus $N_D$ in Si at 300 K. For nondegenerate doping $D_N=(kT/q){\mu }_n$, so the curve has the same shape as ${\mu }_n$ vs $N_D$ (Fig. 3.5): flat at low doping (lattice-scattering limited), then falling as impurity scattering grows. Answer: sketch (c).

(8) Donor in the bonding model: a group-V atom (five valence electrons) substituting for Si; four electrons form bonds, the fifth is a weakly bound extra electron orbiting the ion core (drawn as an extra, unpaired electron on that atom).

(9) Freeze-out in band-diagram language: as $T\to 0$ K the electrons in the conduction band (that came from the donors at $E_D$, just below $E_C$) lose thermal energy and drop back onto the donor level $E_D$; no electrons remain in $E_C$. (Sketch: $E_C$ empty, $E_D$ filled with electrons, $E_V$ filled.)

(10) Resistivities:

${\rho }_n=\frac{1}{q{\mu }_n{N}_D},{\rho }_p=\frac{1}{q{\mu }_p{N}_A}.$

Because ${\mu }_n>{\mu }_p$ in a given semiconductor at a given temperature, for $N_D=N_A$ we get ${\rho }_p>{\rho }_n$: the $n$-type resistivity is smaller.

(11) Recombination via R-G centres: an electron from $E_C$ drops to the trap level $E_T$ (near midgap), then falls from $E_T$ into $E_V$ (equivalently, the trap captures a hole). Sketch: $E_C$, dashed $E_T$, $E_V$ with two downward arrows.

(12) Drift velocity is the average electron or hole velocity resulting from an applied electric field. At low fields $v_d=\mu \mathcal{E}$, with $\mu$ the mobility.

II. Interpretation of an energy band diagram

The diagram (figure lost in OCR) is for a Si device at 300 K with a single flat $E_F$. From the answer key: $E_C$ and $E_V$ are flat on the ends and drop linearly with slope $E_G/L$ over the middle region $L/3\le x\le 2L/3$ (total drop $E_G/3$), and $E_F$ approaches a band edge near $x=L$. Where numeric values are needed I follow the answer key’s stated assumptions.

(13) $V=-E_i/q$: the potential has the shape of the band diagram turned upside down. Answer: (d).

(14) $\mathcal{E}=\frac{1}{q}\frac{d{E}_i}{dx}$ is proportional to the band slope: zero, constant, zero. Answer: (e).

(15) Equilibrium prevails because $E_F$ is invariant with position. Answer: (a).

(16) Degenerate where $E_F$ is at or within a few $kT$ of a band edge: near $x=L$. Answer: (c).

(17) At $x=x_2$ the Fermi level is $E_G/3$ from the band edge, hence $E_G/2-E_G/3=E_G/6$ from midgap:

$|E_i-E_F|=\frac{E_G}{2}-\frac{E_G}{3}=\frac{E_G}{6}$

$\text{concentration}=n_i{e}^{E_G/(6kT)}=10^{10}{e}^{1.12/(6\times 0.0259)}=10^{10}{e}^{7.21}=1.35\times 10^{13}\mathrm{c}{\mathrm{m}}^{-3}.$

Answer: (b). (The key is applied as printed; the minority density would be about $n_i^2/1.35\times 10^{13}\approx 7.4\times 10^6\mathrm{c}{\mathrm{m}}^{-3}$, which is the distractor (a).)

(18) Equilibrium implies no net current: $J_N=0$. Answer: (a).

(19) At the point where $E_i=E_F$ we have $p=n_i$. The field in the sloped region:

$\mathcal{E}=\frac{1}{q}\frac{\Delta E_i}{\Delta x}=\frac{1}{q}\frac{E_G/3}{L/3}=\frac{E_G}{qL}$

$J_P{|}_{drift}=q{\mu }_{p}p\mathcal{E}=q{\mu }_p{n}_i\frac{E_G}{qL}=\frac{{\mu }_p{n}_i{E}_G}{L}.$

Answer: (b).

(20) Hole kinetic energy is the distance from the hole’s energy (drawn on the diagram) to the valence-band edge, $E_G/3$ per the key. Answer: (c).

III. Problem solving

An $n$-type Si bar of length $L$ is maintained at room temperature; boundary conditions $\Delta p_n(0)=\Delta p_{n0}$ and $\Delta p_n(L)=0$; steady state, no photogeneration, $\Delta p_{n0}\le n_0$; $N_D=10^{15}\mathrm{c}{\mathrm{m}}^{-3}$ (recovered from the answer key).

(21) Equilibrium holes:

$n_0\approx N_D=10^{15}\mathrm{c}{\mathrm{m}}^{-3}$ $p_0=\frac{n_i^2}{n_0}=\frac{10^{20}}{10^{15}}=10^5\mathrm{c}{\mathrm{m}}^{-3}.$

Answer: (c).

(22) $\Delta p_n{|}_{max}=\Delta p_{n0}\le n_0$, so low-level injection holds. Answer: (a).

(23) The minority-carrier diffusion equation is

$\frac{\partial \Delta p_n}{\partial t}=D_P\frac{{\partial }^2\Delta p_n}{\partial x^2}-\frac{\Delta p_n}{{\tau }_p}+G_L.$

Steady state ($\partial /\partial t=0$) and no photogeneration ($G_L=0$) leave

$0=D_P\frac{d^2\Delta p_n}{d{x}^2}-\frac{\Delta p_n}{{\tau }_p}⟺0=\frac{d^2\Delta p_n}{d{x}^2}-\frac{\Delta p_n}{L_P^2}.$

Answer: (e).

(24) Second-order linear ODE with characteristic roots $\pm 1/L_P$:

$\Delta p_n(x)=A{e}^{-x/L_P}+B{e}^{x/L_P},L_P^2=D_P{\tau }_p.$

Answer: (a).

(25) The boundary conditions are those stated for the bar: $\Delta p_n(0)=\Delta p_{n0}$ and $\Delta p_n(L)=0$. Answer: (c).

Completing the problem (bonus). Applying them:

$A+B=\Delta p_{n0},A{e}^{-L/L_P}+B{e}^{L/L_P}=0$

$\Delta p_n(x)=\Delta p_{n0}\frac{\sinh [(L-x)/L_P]}{\sinh (L/L_P)}.$

For $L\ll L_P$ this becomes the straight line $\Delta p_{n0}(1-x/L)$, and for $L\gg L_P$ it becomes $\Delta p_{n0}{e}^{-x/L_P}$.

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End of Part I supplement. Part II (Chapter 5, pn junctions) begins on the next page of the source.